In most of today's operating system architectures, device drivers are tightly coupled with other kernel components. In such systems, a fault caused by a malicious or faulty device driver often leads to complete system failure, thereby reducing the overall reliability of the system. Even though a majority of the operating systems provide protection mechanisms at the user level, they do not provide the same level of protection for kernel components. Using virtualization, device drivers can be executed in separate, isolated virtual machines, called driver domains. Such domains provide the same level of isolation to device drivers as operating systems provide to user level applications. Domain-based isolation has the advantage that it is compatible with existing drivers and transparent to the kernel. However, domain-based isolation incurs significant performance overhead due to the necessary interdomain communication. This thesis investigates techniques for reducing this overhead. The key idea is to replace the interrupt-based notification between domains with a spinning-based approach, thus trading CPU capacity for increased throughput. We implemented a prototype, called the Isolated Device Driver system (IDDR), which includes front-end and back-end drivers and a communication module. We evaluated the impact of our optimizations for a variety of block devices. Our results show that our solution matches or outperforms Xen's isolated driver domain in most scenarios we considered. / Master of Science

New peripheral devices are being developed at an ever increasing rate. Before such accessories can be used in the UNIX environment (UNIX is a trademark of Bell Laboratories), they must be able to communicate with the operating system. This involves writing a device driver for each device. In order to do this, very detailed knowledge is required of both the device to be integrated and the version of UNIX to which it will be attached. The process is long, detailed and prone to subtle problems and errors. This paper presents a menu-driven utility designed to simplify and accelerate the design and implementation of UNIX device drivers by freeing developers from many of the implementation specific low-level details.

Thesis (M. Sc. (Computer Science))--Rhodes University, 2004.

Thesis (MSc)--Stellenbosch University, 2000. / ENGLISH ABSTRACT: Users are not supposed to modify an operating system kernel, but it is often necessary to add a device driver for a new peripheral device. Device driver development is a difficult and time-consuming process that must be performed by an expert. Drivers are difficult to debug and a malfunctioning driver could cause the operating system to crash. Ways are therefore needed to make the development of device drivers safer and easier. A number of different device driver development methods are examined in this thesis. An existing micro-kernel that supports in-kernel device drivers as well as extensible device drivers has been modified to support user-level and loadable drivers. These extensions ensured that all the development methods were implemented in the same environment and a comparison could thus be made on a fair basis. A comparison of the different methods with respect to the efficiency of the resulting device driver, as well as the ease of the development process, is presented. / AFRIKAANSE OPSOMMING: Gebruikers is nie veronderstelom aan 'n bedryfstelsel te verander nie, maar tog is dit gereeld nodig om 'n toesteldrywer vir 'n nuwe randapparaat by te voeg. Die ontwikkeling van 'n toesteldrywer is 'n tydrowende en moeilike proses en moet deur 'n kundige aangepak word. Toesteldrywers is moeilik om te ontfout en kan deur verkeerde werking die hele stelsel tot stilstand bring. Daar is dus tegnieke nodig om die ontwikkeling van toestelhanteerders makliker en veiliger te maak. 'n Aantal verskillende ontwikkelingsmetodes vir toesteldrywers word in hierdie tesis ondersoek. 'n Bestaande mikro-kern wat in-kern, sowel as uitbreibare toesteldrywers ondersteun, is aangepas om gebruikersvlak en laaibare toestelhanteerders te ondersteun. Hierdie uitbreiding het verseker dat al die ontwikkelingsmetodes in dieselfde omgewing geïmplementeer is. Dit was dus moontlik om die metodes op 'n regverdige grondslag te vergelyk. Die vergelyking is gedoen ten opsigte van die effektiwiteit van die resulterende toesteldrywer sowel as die moeilikheidsgraad van die ontwikkelingsproses.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / This paper illustrates a device driver implementation used to support a PC compatible telemetry device. Device requirements included operation on Windows NT 4.0, Windows 95, Windows NT 5.0 and Windows 98 platforms. A single device driver was not possible due to the differences between driver requirements on the various operating systems. The Windows Driver Model (WDM) was considered for NT 5.0 and Win98, however, NT 4.0 and Win95 does not support the WDM. To minimize software development and support efforts, it was clear that an architecture compatible to both WDM, NT 4.0 and Windows 95 needed to be developed. The resulting layered device driver architecture provides a common upper interface and uses a register based model to describe the hardware at the lower interface. The common upper interface is compatible with all of the target operating systems and presents a consistent Applications Programming Interface (API) for the telemetry application developer. The lower interface is specific for each platform but contains minimal device specific functionality. A simple register I/O driver is easily implemented using all of the target operating systems. The layered architecture and register based interface to the hardware results in a multiple operating system code set which differs only at the lowest layer.

This dissertation is dedicated to the problem of device driver reliability. Software defects in device drivers constitute the biggest source of failure in operating systems, causing significant damage through downtime and data loss. Previous research on driver reliability has concentrated on detecting and mitigating defects in existing drivers using static analysis or runtime isolation. In contrast, this dissertation presents an approach to reducing the number of defects through an improved device driver architecture and development process. In analysing factors that contribute to driver complexity and induce errors, I show that a large proportion of errors are due to two key shortcomings in the device-driver architecture enforced by current operating systems: poorly-defined communication protocols between drivers and the operating system, which confuse developers and lead to protocol violations, and a multithreaded model of computation, which leads to numerous race conditions and deadlocks. To address the first shortcoming, I propose to describe driver protocols using a formal, state-machine based, language, which avoids confusion and ambiguity and helps driver writers implement correct behaviour. The second issue is addressed by abandoning multithreading in drivers in favour of a more disciplined event-driven model of computation, which eliminates most concurrency-related faults. These improvements reduce the number of defects without radically changing the way drivers are developed. In order to further reduce the impact of human error on driver reliability, I propose to automate the driver development process by synthesising the implementation of a driver from the combination of three formal specifications: a device-class specification that describes common properties of a class of similar devices, a device specification that describes a concrete representative of the class, and an operating system interface specification that describes the communication protocol between the driver and the operating system. This approach allows those with the most appropriate skills and knowledge to develop specifications: device specifications are developed by device manufacturers, operating system specifications by the operating system designers. The device-class specification is the only one that requires understanding of both hardware and software-related issues. However writing such a specification is a one-off task that only needs to be completed once for a class of devices. This approach also facilitates the reuse of specifications: a single operating-system specification can be combined with many device specifications to synthesise drivers for multiple devices. Likewise, since device specifications are independent of any operating system, drivers for different systems can be synthesised from a single device specification. As a result, the likelihood of errors due to incorrect specifications is reduced because these specifications are shared by many drivers. I demonstrate that the proposed techniques can be incorporated into existing operating systems without sacrificing performance or functionality by presenting their implementation in Linux. This implementation allows drivers developed using these techniques to coexist with conventional Linux drivers, providing a gradual migration path to more reliable drivers.

Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (p. 137-154).

Made available in DSpace on 2014-06-12T16:00:24Z (GMT). No. of bitstreams: 2 arquivo6554_1.pdf: 3066452 bytes, checksum: 91820a83661287c92ba4438dd8c7a4d7 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2007 / Os dispositivos lógicos programáveis, FPGAs (Field Programmable Gate Arrays) há algum tempo têm sido uma tecnologia interessante para prototipação de circuitos digitais. Porém, esta realidade tem mudado à medida que a capacidade computacional destes dispositivos tem aumentado e o custo diminuído. Além disso, os FPGAs atuais podem utilizar menos energia que uma CPU convencional utilizaria para realizar a mesma computação. Outra característica, que traz grandes possibilidades, é a capacidade de reconfiguração em tempo de execução (reconfiguração dinâmica). Todos estes avanços permitiram a utilização dos FPGAs não só em aplicações típicas como sistemas embarcados mas também em sistemas de alto desempenho, que realizam processamento massivo de dados. Contudo, apesar das diversas vantagens apresentadas, esta tecnologia ainda não é largamente utilizada para realizar computação. Várias são as razões para isso, entre elas a exigência de um mínimo conhecimento em eletrônica digital para possibilitar o desenvolvimento dos IP-Cores; a complexidade do processo de desenvolvimento destes sistemas; os custos elevados com licenças das ferramentas e com as plataformas de desenvolvimento e a pouca portabilidade das aplicações desenvolvidas. O objetivo deste trabalho é prover uma plataforma reconfigurável que seja capaz, através de um sistema operacional e de maneira eficiente, gerenciar os recursos oferecidos pelos FPGAs. A plataforma proposta recebeu o nome de Aquarius II e foi baseada na plataforma Aquarius desenvolvida no CIn-UFPE. A arquitetura desta plataforma é híbrida e consiste de um FPGA Stratix-II da Altera responsável pelo controle da reconfiguração e tráfego dos dados e de um FPGA Virtex-II da Xilinx que é o elemento reconfigurável propriamente dito. Foram incorporados a esta plataforma um módulo de comunicação (IPCommCore) que é responsável pelo tráfego de dados do sistema operacional para a memória do dispositivo reconfigurável, um device driver para que o sistema operacional uCLinux possa controlar a comunicação através deste módulo e também foi definida uma interface de comunicação padrão para os cores reconfiguráveis que vierem a ser implementados. Para validar esta interface foi implementado e validado um core multiplicador para o Virtex-II utilizado como estudo de caso. Esta plataforma permitirá que sejam realizadas pesquisas em áreas que buscam se beneficiar desta tecnologia, como desenvolvimento de sistemas embarcados e sistemas de alta performance. O desenvolvimento de sistemas computacionais que utilizam hardware reconfigurável em sua arquitetura ainda é pouco comum e complexo. No entanto, propostas como a apresentada neste trabalho procuram solucionar ou atenuar os problemas citados e mudar sensivelmente esta realidade tornando viáveis e mais populares soluções que utilizam esta tecnologia

Efficient memory access is critical for computing systems, yet the CPU's management of data transfers can create bottlenecks. To counter this, most advanced high-throughput systems utilize Direct Memory Access (DMA) controllers, where peripherals (such as network interfaces and USB devices) can access memory independently of the CPU, improving transfer speeds. However, this bypass also introduces security vulnerabilities if the DMA controller is not configured correctly, as DMA devices may be used to overwrite critical data or leak information. This thesis proposes a method to represent complex DMA driver source code as an abstract mathematical model in the formal analysis tool HOL4 (where users can define models and prove properties about them with HOL4 and checking the correctness of the proofs). This model enables the formal verification of the DMA driver source code's critical properties like memory isolation, initial configurations, and many more. Additionally, the thesis introduces a methodology to convert the verified HOL4 models into executable C source code, thus obtaining a formally verified C source code. The synthesized code is evaluated against the original driver source code by emulating the DMA operation in software and using fuzzing techniques for any compile and runtime errors. This validates the approach, demonstrating that converting a C driver source code into a HOL4 model and then back into C source code after verification yields a formally verified C source code. This thesis applies this methodology to DMA controllers for four devices namely Intel 8237a, Intel IXGBE x550 Ethernet Controller, MPC 5200 SoC, and STM32 DMAC. / Master of Science / This thesis addresses the critical issue of ensuring secure memory access in computing systems, focusing on Direct Memory Access (DMA) controllers. DMA devices can bypass the CPU to access a range of memory directly, enhancing transfer speeds but introducing security vulnerabilities like overwriting or leaking critical data if not configured correctly. This thesis proposes a method to model complex DMA driver source codes such that they can be rigorously analyzed with computer assistance. This approach is significant as it provides a structured methodology for analyzing DMA driver source code, reducing the risk of errors and vulnerabilities. The thesis also proposes a method to convert the abstract representation into executable source code, thus improving the reliability and security of DMA operations in computing systems.

New hardware devices are continually being released to the public by hardware manufactures around the world. For these new devices to be usable under a PC operating system, device drivers that extend the functionality of the target operating system have to be constructed. This work examines and compares the device driver architectures currently in use by two of the most widely used operating systems, Microsoft’s Windows and Linux. The IEEE1394 (high speed serial bus) device driver stacks on each operating system are examined and compared as an example of a major device driver stack implementation, including driver requirements for the upcoming IEEE1394.1 bridging standard.