The processing and properties of novel polymer-based nano-composite (PNC) dielectrics for capacitor applications has been studied. PNCs were fabricated via a vacuum based deposition technique and their micro/nano-structure, chemical and dielectric properties investigated. After process development and optimisation, co-deposited Al and nylon-6 PNCs had a dielectric constant k∼7 at an approximate Al volume fraction of 0.3 that agreed with analytical predictions if it was assumed that the Al transformed to an oxide in-situ and/or after deposition. The significant effect of absorbed water vapour and temperature on PNC dielectric properties was revealed using different types of post-deposition heat treatment. Alternately-deposited PNCs consisting of Al or Ag 2-20 nm layers sandwiched between nylon-6 layers were fabricated in which the overall PNC Al or Ag volume fraction was controlled by varying the nominal Al or Ag layer thickness. Ag layers comprised of discrete nano-islands that produced a nano-capacitor network effect that increased k to ∼11. In the case of Al layers, when the layer thickness was ≥ 5 nm, corresponding to a nominal volume fraction of 0.1, Al (core)-oxide (shell) nanoparticles were formed and the PNC dielectric constant increased to ∼19. The detailed nano-structure of the core-shell particles was studied using various types of transmission electron microscopy (TEM), and the elevations in dielectric constant ascribed to multiple-interface polarisation effects dependent on the formation of the core-shell structure. PNCs based on alternate deposition of Ti sandwiched in nylon-6, and then both Ti and Ag in nylon-6 were also fabricated, with k reaching ∼73 for Ag+Ti/nylon-6 PNCs. As well as Ti-based core (metal)-shell (oxide) particles, the Ag volume fraction was sufficiently high in the 10 nm nylon-6 layers to again form a nano-capacitor network that contributed to the overall device capacitance and effective dielectric constant. Again, various types of high magnification TEM were critical in resolving the Ti-based core-shell structure and its role in high-k behaviour. The vacuum-based alternate deposition technique has been developed to offer ease of operation, reliability, flexibility and applicability to chemically different filler and matrix systems in the fabrication of high-k PNC based capacitors, in which high-k performance relies critically on the formation of core (metal)-shell (oxide) particles in both Al and Ti based systems.

We determined the dielectric function of the alloy system (AlxGa1−x)2O3 by spectroscopic ellipsometry in the wide spectral range from 0.5 eV to 8.5 eV and for Al contents ranging from x = 0.11 to x = 0.55. For the composition range x<0.4, we observe single phase material in the b-modification and for larger Al content also the occurrence of γ-(Al,Ga)2O3. We derived spectra of the refractive index and the absorption coefficient as well as energy parameters of electronic bandband transitions by model analysis of the dielectric function. The dependence of the dielectric functions lineshape and the energy parameters on x is highly continuous, reflecting theoretical expectations. The data presented here provide a basis for a deeper understanding of the electronic properties of this material system and may be useful for device engineering.

We determined the dielectric function of the alloy system (InxGa1−x)2O3 by spectroscopic ellipsometry in the wide spectral range from 0.5 eV to 8.5 eV and for In contents ranging from x = 0.02 to x = 0.61. The predicted optical transitions for binary, monoclinic β-Ga2O3, and cubic bcc-In2O3 are well reflected by the change of the dielectric functions’ lineshape as a function of the In content. In an intermediate composition range with phase-separated material (x ≈ 0.3…0.4), the lineshape differs considerably, which we assign to the presence of the high-pressure rhombohedral InGaO3-II phase, which we also observe in Raman experiments in this range. By model analysis of the dielectric function, we derived spectra of the refractive index and the absorption coefficient and energy parameters of electronic band-band transitions. We discuss the sub-band gap absorption tail in relation to the influence of the In 4d orbitals on the valence bands. The data presented here provide a basis for a deeper understanding of the electronic properties of this technologically important material system and may be useful for device engineering.

Résumé: Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal court, effet de porteurs chauds et fiabilité des oxydes de grille. Le transistor à un électron (SET) fait partie des composants émergents candidats pour remplacer les transistors CMOS ou pour constituer une technologie complémentaire à celle-ci. Ce travail de thèse traite de l’amélioration des caractéristiques électriques du transistor à un électron en optimisant ses jonctions tunnel. Cette optimisation commence tout d’abord par une étude des modes de conduction à travers la jonction tunnel. Elle se conclut par le développement d’une jonction tunnel optimisée basée sur un empilement de matériaux diélectriques (principalement Al[indice inférieur 2]O[indice inférieur 3], H[florin]O[indice inférieur 2] et TiO[indice inférieur 2]) ayant des propriétés différentes en termes de hauteurs de barrières et de permittivités relatives. Ce manuscrit présente, la formulation des besoins du SET et de ses jonctions tunnel, le développement d’outils de simulation appropriés - basés sur les Matrices de transmission - pour la simulation du courant des jonctions tunnel du SET, l’identification des stratégies d’optimisation de ces dernières, grâce aux simulations et finalement l’étude expérimentale et l’intégration technologique des jonctions tunnel optimisées dans le procédé de fabrication de SET métallique en utilisant la technique de dépôt par couches atomiques (ALD). Ces travaux nous ont permis de prouver l’intérêt majeur de l’ingénierie des jonctions tunnel du SET pour accroitre son courant à l’état passant, réduire son courant de fuite et étendre son fonctionnement à des températures plus élevées. / Abstract: Today, several technological barriers and physical limitations arise against the miniaturization of the CMOS: leakage current, short channel effects, hot carrier effect and the reliability of the gate oxide. The single electron transistor (SET) is one of the emerging components most capable of replacing CMOS technology or provide it with complementary technology. The work of this thesis deals with the improvement of the electrical characteristics of the single electron transistor by optimizing its tunnel junctions. This optimization initially starts with a study of conduction modes through the tunnel junction. It concludes with the development of an optimized tunnel junction based on a stack of dielectric materials (mainly Al[subscript 2]O[subscript 3], H[florin]O[subscript 2] and TiO[subscript 2]), having different properties in terms of barrier heights and relative permittivities. This document, therefore, presents the theoretical formulation of the SET’s requirements and of its tunnel junctions, the development of appropriate simulation tools - based on the transmission matrix model- for the simulation of the SET tunnel junctions current, the identification of tunnel junctions optimization strategies from the simulations results and finally the experimental study and technological integration of the optimized tunnel junctions into the metallic SET fabrication process using the atomic layer deposition (ALD) technique. This work allowed to démonstrate the significance of SET tunnel junctions engineering in order to increase its operating current while reducing leakage and improving its operation at higher temperatures.

Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal court, effet de porteurs chauds et fiabilité des oxydes de grille. Le transistor à un électron (SET) fait partie des composants émergents candidats pour remplacer les transistors CMOS ou pour constituer une technologie complémentaire à celle-ci. Ce travail de thèse traite de l’amélioration des caractéristiques électriques du transistor à un électron en optimisant ses jonctions tunnel. Cette optimisation commence tout d’abord par une étude des modes de conduction à travers la jonction tunnel. Elle se conclut par le développement d’une jonction tunnel optimisée basée sur un empilement de matériaux diélectriques (principalement Al2O3, HfO2 et TiO2) ayant des propriétés différentes en termes de hauteurs de barrières et de permittivités relatives. Ce manuscrit présente, la formulation des besoins du SET et de ses jonctions tunnel, le développement d’outils de simulation appropriés - basés sur les matrices de transmission - pour la simulation du courant des jonctions tunnel du SET, l’identification des stratégies d’optimisation de ces dernières, grâce aux simulations et finalement l’étude expérimentale et l’intégration technologique des jonctions tunnel optimisées dans le procédé de fabrication de SET métallique en utilisant la technique de dépôt par couches atomiques (ALD). Ces travaux nous ont permis de prouver l’intérêt majeur de l’ingénierie des jonctions tunnel du SET pour accroitre son courant à l’état passant, réduire son courant de fuite et étendre son fonctionnement à des températures plus élevées. / Today, several technological barriers and physical limitations arise against the miniaturization of the CMOS: leakage current, short channel effects, hot carrier effect and the reliability of the gate oxide. The single electron transistor (SET) is one of the emerging components most capable of replacing CMOS technology or provide it with complementary technology. The work of this thesis deals with the improvement of the electrical characteristics of the single electron transistor by optimizing its tunnel junctions. This optimization initially starts with a study of conduction modes through the tunnel junction. It concludes with the development of an optimized tunnel junction based on a stack of dielectric materials (mainly Al2O3, HfO2 and TiO2), having different properties in terms of barrier heights and relative permittivities. This document, therefore, presents the theoretical formulation of the SET’s requirements and of its tunnel junctions, the development of appropriate simulation tools - based on the transmission matrix model- for the simulation of the SET tunnel junctions current, the identification of tunnel junctions optimization strategies from the simulations results and finally the experimental study and technological integration of the optimized tunnel junctions into the metallic SET fabrication process using the atomic layer deposition (ALD) technique. This work allowed to demonstrate the significance of SET tunnel junctions engineering in order to increase its operating current while reducing leakage and improving its operation at higher temperatures.

Recently, high-κ materials have become the focus of research and been extensively utilized as the gate dielectric layer in aggressive scaled complementary metal-oxide-semiconductor (CMOS) technology. Hafnium dioxide (HfO2) is the most promising high-κ material because of its excellent chemical, thermal, mechanical and dielectric properties and also possesses good thermodynamic stability and better band offsets with silicon. Hence, HfO2 has already been used as gate dielectric in modern CMOS devices. For future technologies, it is very difficult to scale the silicon transistor gate length, so it is a necessary requirement of replacing the channel material from silicon to some high mobility material. Two-dimensional layered materials such as graphene and molybdenum disulfide (MoS2) are potential candidates to replace silicon. Due to its planar structure and atomically thin nature, they suit well with the conventional MOSFET technology and are very stable mechanically as well as chemically. HfO2 plays a vital role as a gate dielectric, not only in silicon CMOS technology but also in future nano-electronic devices such as graphene/MoS2 based devices, since high-κ media is expected to screen the charged impurities located in the vicinity of channel material, which results in enhancement of carrier mobility. So, for sustenance and enhancement of new technology, extensive study of the functional materials and its processing is required. In the present work, optimization of HfO2 thin films for gate dielectric applications in Nano-electronic devices using electron beam evaporation is discussed. HfO2 thin films have been optimized in two different thickness regimes, (i) about 35 nm physical thicknesses for back gate oxide graphene/MoS2 transistors and (ii) about 5 nm physical thickness to get Equivalent Oxide Thickness (EOT) less than 1 nm for top gate applications. Optical, chemical, compositional, structural and electrical characterizations of these films have been done using Ellipsometry, X-ray Photoelectron Spectroscopy (XPS), Rutherford Back Scattering (RBS), X-ray Diffraction (XRD), Capacitance-Voltage and Current-Voltage characterization techniques. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post deposition annealing (PDA) and post metallization annealing (PMA) in forming gas ambient (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. A high density film (ρ=8.2 gram/cm3, 85% of bulk density) with high dielectric constant of κ=19 and leakage current density of J=2.0×10-6 A/cm2 at -1 MV/cm has been achieved at optimized deposition conditions. Bilayer graphene on HfO2/Si substrate has been successfully identified and also transistor has been fabricated with HfO2 (35 nm) as a back gate. High transconductance compared to other back gated devices such as SiO2/Si and Al2O3/Si and high mobility have been achieved. The performance of back gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 SCCM and 20 SCCM has been evaluated. It is found that the device on the film deposited at 3 SCCM O2 flow rate shows better properties. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. MoS2 layers on the optimized HfO2/Si substrate have been successfully identified and transistor has been fabricated with HfO2 (32 nm) as a back gate. The device is switching at lower voltages compared to SiO2 back gated devices with high ION/IOFF ratio (>106). The effect of film thickness on optical, structural, compositional and electrical properties for top gate applications has been studied. Also the effect of gate electrode material and its processing on electrical properties of MOS capacitors have been studied. EOT of 1.2 nm with leakage current density of 1×10-4 A/cm2 at -1V has been achieved.