A computer simulation program was developed to simulate the Virginia Tech low pressure steam heating system. Based on the total heat available to the buildings and the buildings' relative transmission heat losses, this program will determine the distribution of the heat produced by the steam plant and determine the conditions of the steam at the buildings and along the pipeline. The above distribution of heat consists of heat lost from the pipeline and heat delivered to the buildings. This program was used to perform a preliminary performance evaluation of the steam heating system during the 1983-84 heating season, and for the coldest day (12/24/83) and day of maximum steam load (2/29/84) in particular. During this heating season 2.397 x 10¹¹ Btu was delivered by the steam plant to the buildings. Also, about 3% of the total heat delivered by the steam plant was lost through the pipeline. To enhance the usefulness of this program two actions were recommended. First, the steam pipeline and the buildings should be instrumented to allow for verification of the program results. Second, in order to produce more accurate results the program's data should be based on more accurate measurements of the pipeline characteristics and the building heating loads. / Master of Science

A hydrostatic drive test stand was constructed to aid in the instruction of the characteristics of hydrostatic transmissions and to develop a time-varying load in a shaft to compare torque transducers. A mathematical model of the device was derived using the bond graph approach and was implemented using the Advanced Continuous Simulation Language (ACSL). The test stand was used to obtain experimental data to try to refine the model parameters. To facilitate the measurement of system flows, a microprocessor-based digital flow indicator was developed. Steady-state tests were performed at various constant pump swashplate angles; for the dynamic tests, the pump swashplate angle was cycled from zero degrees to 6.5 degrees. / Master of Science / incomplete_metadata

This paper presents a hierarchical modeling method that can be used to simulate a Flexible Manufacturing System (FMS) at all levels of detail. The method was developed specifically to aid the software development needed for the hierarchy of computers that are present in an FMS. The method was developed by modeling an existing FMS. The models developed of the existing FMS are described in detail to provide an example of how to model other FMSs. The basic building blocks needed for designing other FMSs with this modeling method are provided. The models were written in the SIMAN simulation language. SIMAN was found to be an easy language to use for the hierarchical modeling of FMSs. / M.S.

The purpose of the thesis was to investigate the influence communication architecture decisions have on the performance of a simulation system with distributed components. In particular, the objective was to assess the relative importance of factors affecting reliability and variability of an external data interface to the performance of the simulation, as compared to factor within the simulation itself.

No description available.

The purpose of this project was to describe a novel design approach for a digital computer peripheral controller, then design and construct a case study controller. This document consists of three chapters and an appendix. Chapter II presents the design approach chosen; a variation to a design presented by Charles R. Richards in an article published in Electronics magazine. Richards' approach consists of a finite state machine circuitry controlling all the functions of a controller. The variation to Richards' approach consists of considering the various logically independent processes which a controller carries out and assigning control of each process to a separate finite state machine. The appendix contains the documentation of the design and construction of the controller.

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING / Bibliography: leaf 22. / by Inwhan Choi. / B.S.

Research was supported by the Energy Research and Development Administration as part of a contract with Arthur D. Little, inc.

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-10T11:21:32Z (GMT). No. of bitstreams: 1 Sigrist_ThiagoMassariolli_M.pdf: 1159366 bytes, checksum: 1b73082be801a7391d4d5176c6e49207 (MD5) Previous issue date: 2007 / Resumo: O surgimento dos SoCs (Systems-on-Chip) levou ao desenvolvimento das metodologias de projeto baseadas em TLM (Transaction-Level Modelling), que oferecem diversas etapas de modelagem intermediárias entre a especificação pura e a descrição sintetizável RTL (Register Transfer Level ), tornando mais tratável o projeto de sistemas dessa complexidade. Levando-se em consideração que esses sistemas geralmente possuem microprocessadores como módulos principais, torna-se desejável o uso de linguagens de descrição de arquiteturas (ADLs ? Architecture Description Languages) como ArchC e suas ferramentas para que seja possível modelar esses processadores e gerar módulos simuladores para eles em uma fração do tempo tradicionalmente gasto com essa tarefa. Porém, ArchC, em sua penúltima versão, a 1.6, possui utilidade limitada para esse fim, pois os simuladores que é capaz de gerar são autocontidos, não sendo facilmente integráveis aos modelos TLM em nível de sistema como um todo. Este trabalho consiste em uma remodelagem da linguagem ArchC e sua ferramenta acsim de modo a acrescentar essa capacidade de integração aos simuladores funcionais interpretados que é capaz de gerar, dando assim origem à versão 2.0 de ArchC / Abstract: The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure specifications and synthesizable RTL (Register Transfer Level ) descriptions, making the complexity of such systems more manageable. Considering that those systems usually have microprocessors as main modules, it is desirable to use architecture description languages (ADLs) like ArchC and its toolkit to model those processors and generate simulator modules for them in a fraction of the time usually spent in that task. However, ArchC, in its previous version, 1.6, has limitations for that use, since the simulators it generates are self-contained, thus hard to integrate to TLM system-level models. This work consists in remodelling ArchC and its acsim tool, adding this ability of integration to its functional interpreted simulators, leading to version 2.0 of ArchC / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-22T19:27:44Z (GMT). No. of bitstreams: 1 Guedes_Marcelo_M.pdf: 3596190 bytes, checksum: cb76d95f3dd3a8542b2e08b6b38550e0 (MD5) Previous issue date: 2012 / Resumo: A dissertação apresenta acSynth, um conjunto de ferramentas integradas que tem por objetivo fornecer uma plataforma aberta de desenvolvimento e síntese de projetos a partir de descrições em ADL ArchC. Como primeiro trabalho, acSynth foi equipado com ferramentas para caracterização de consumo de energia de processadores através do método Tiwari. Isto foi concretizado através da composição das ferramentas PowerSC, acPower e acPowerGen, capacitando acSynth a obter e armazenar informações de consumo de energia. Estes dados podem, então, ser utilizados em simulações em acSim, com geração automática de relatórios em nível ADL. Após a caracterização, é possível distribuir as informações coletadas para evitar reexecutar o fluxo para as mesmas ferramentas e processadores. O trabalho apresenta resultados de caracterização dos processadores MIPS-I Plasma e SPARCv8 Leon3, bem como integração com as ferramentas de síntese da Altera e da Xilinx. Os processadores foram submetidos a testes com os benchmarks acStone, Mibench e Mediabench, com elaboração de relatórios de consumo de energia e gráficos de perfil energético no tempo. Um estudo do erro da caracterização foi apresentado. Para testes com MIPS-I o erro efetivo sobre plataforma Xilinx variou de 0,02% a 61,05%, com 91% dos casos com erro menor ou igual a 30%. Em plataforma Altera o erro efetivo variou de 0,01% a 17,49% com 96% dos casos com erro menor ou igual a 15%. Para testes com SPARCv8 em plataforma Xilinx o erro efetivo variou de 0,14% a 40,66% com 95% dos casos com erro menor ou igual a 20%. Adicionalmente, desenvolveu-se um processador MIPS-I pipelined através do fluxo da ferramenta acRTL. Um histórico do processo com detalhes dos prós e contras é apresentado. Um arquivo com dados de consumo de energia das instruções suportadas foi elaborado. Por fim, energia, área e desempenho foram estudados e comparados ao processador Plasma. As principais contribuições deste trabalho são: interconexão de ferramentas e mostra dos benefícios obtidos com isto; apresentação de uma abordagem de caracterização de consumo de energia de processadores no nível de arquitetura; demonstração de um método funcional para expansão de acSim para abarcar novos aspectos de simulação em alto nível; aplicação prática de acRTL / Abstract: This work presents acSynth, an integrated framework for development and synthesis based on ArchC ADL descriptions. In its first application, acSynth includes characterization tools to allow power consumption analysis for supported processor architectures, through Tiwari's method. The power analysis and characterization tools were achieved by integrating PowerSC, acPower and acPowerGen, allowing acSynth to gather, process and store power consumption data in order to create power reports. This data could then be used in acSim simulations, generating ADL level power analysis reports automatically. We show characterization results for MIPS-I Plasma processor and SPARCv8 Leon3 processor using two different synthesis tools and workflows, Altera and Xilinx. The processors were tested with acStone, Mibench and Mediabench benchmarks, generating power reports and energy consumption profile graphs with energy per time data. We analyzed the error comparing to RTL simulations. The analysis with MIPS-I and Xilinx tool set presented effective error between 0.02% and 61.05%, with 91% of the total number of analyzed cases presenting errors with less than or equal to 30%. Adopting Altera tool set, the effective error was between 0.01% and 17.49% with 96% of the total number of analyzed cases showing error with less than or equal to 15%. For SPARCv8 architecture, using Xilinx tool set, the effective error ranged between 0.14% and 40.66% with 95% of the total number of analyzed cases presenting errors with less than or equal to 20%. Furthermore, a MIPS-I pipelined processor was developed using the acRTL workflow. The complete development is detailed in this dissertation, highlighting the method advantages and disadvantages. The new processor power consumption data was collected and an acSynth power database generated. Finally, power, area and performance was investigated and compared to the stable processor Plasma. The main contributions of the present dissertation are: ArchC tool set integration showing the benefits in high level analysis; introduction of a new power characterization method in architecture level, expanding ArchC environment; design of a practical method to expand the acSim analysis and behavior, covering new high level simulation aspects; the practical use of acRTL / Mestrado / Ciência da Computação / Mestre em Ciência da Computação