Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demandson the analog to digital converter. It is therefore important in the design of theanalog to digital converter to reduce noise and offset as much as possible. That isalso what this analysis is going to consider but in a comparator which is a crucialpart of the analog to digital converter. The comparator consists of a preamplifierand a latch and it is the preamplifier that will be studied here. The analog todigital converter in consider is of PSAR structure. Some other structures will alsobe mentioned in the first part together with some noise theory.

<p>Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demandson the analog to digital converter. It is therefore important in the design of theanalog to digital converter to reduce noise and offset as much as possible. That isalso what this analysis is going to consider but in a comparator which is a crucialpart of the analog to digital converter. The comparator consists of a preamplifierand a latch and it is the preamplifier that will be studied here. The analog todigital converter in consider is of PSAR structure. Some other structures will alsobe mentioned in the first part together with some noise theory.</p><p> </p><p> </p>

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

As neural interfaces continue to progress toward practical applications, there is increased demand for smaller, more efficient and cost effective devices. Event related potentials (ERPs) have recently been demonstrated to be reliable for practical communication in disabled individuals using the P300 Speller paradigm. With the objective of simplifying the processing of ERPs in order to minimize the hardware/computational requirements, and therefore the power consumption (for increased battery life for wireless, etc.), this study examines the effects of the analog-to-digital converter amplitude quantization on the ERP classification accuracy for the P300 Speller.

Due to the rapid growth of the communication market, a large amount of research is in process toward a high speed and high resolution sigma-delta A/D converter. This dissertation focuses on the design of a single-stage sigma-delta A/D converter with very low oversampling ratio for the wireless application. An architecture for a multibit single-stage delta-sigma A/D converter with two-step quantization is proposed. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine DEM and DAC is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise-shaped by using a digital requantization (REQ) algorithm. A second-order single-stage sigma-delta A/D converter with 8-bit two-step inner quantization is proposed in this dissertation, which employs the feed-forward branches to reduce the integrator output swing. The proposed modulator is implemented with TSMC 0.25 μm mixed-signal process, using the switched-capacitor circuit. The measured system achieves the dynamic range of 70 dB under an oversampling ratio of 16 with the REQ algorithm reducing the noise floor in the signal bandwidth by 20 dB.

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International Telemetering Conference Proceedings / October 22-25, 1984 / Riviera Hotel, Las Vegas, Nevada / Blood pressure signals recorded continuously in ambulatory patients using the Oxford system were analyzed by an IBM 370 computer in order to obtain beat by beat systolic and diastolic blood pressure along 24 hour blood pressure recordings. The method of digitizing the signal and the analysis of the sphygmogram are presented and discussed. Synthesis of the several thousands data obtained in 24 hour recordings and plotting of the data for clinical purposes and pharmacological studies are also reported.

This thesis reports on the design and evaluation of a microprocessor-controlled, high-speed analog-to-digital converter. The processor supervises and manages the digital conversion, split-phase encoding (Manchester) and framing of the input signal. This converter is designed to be applied in an underwater package which will serially transmit sensor data over a fiber optic link to a shore station. This intelligent sensor will provide for ease of future system enhancements. An example would be the implementation of one package to multiplex several analog channels from a local sensor network over the single fiber optic link to the shore station. Keywords: Analog-to-Digital converter, Digital conversion, Split phase encoding, and Manchester. (r.h.) / http://archive.org/details/microprocessorco00schl / U.S. Coast Guard (U.S.C.G.) author.

The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative. / QC 20120528