International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / The monitoring of multi phase 400 Hz aircraft power includes monitoring the phase voltages, currents, real powers, and frequency. This paper describes the design of a multi channel card that uses digital signal processing (DSP) to measure these parameters on a cycle by cycle basis. The card measures the average, peak, minimum cycle, and maximum cycle values of these parameters.

This paper proposes a sensorless control construction adapting to different speed with DSP2407 as the signal processing control core for rotation compressor. The sensorless control method obtains the rotor position by detecting the back electromotive force signals directly, then obtains better communications and the speed estimation by using digital signal which controlling power switches. Finally ,it carries out speed feedback control and current feedback control to improvt efficiency. Comparing adaptive-step control with traditional-step control and six-step control , the experiment result shows that adaptive-step control has better efficiency and lower vibration.

The DSP is used as the control kernel in this thesis, proposing a method of sensorless and variable speed driving with current feedback for the DC compressor. By detecting the back electromotive force signals directly, the information of rotor position can be obtained, the commutation process and the speed estimation can also be achieved. Combining the current feedback method, the sinusoidal commutation with sensorless control makes the motor lower speed ripple and higher rotating efficiency. The results show that the sinusoidal commutation approach has the advantages of higher efficiency and less speed ripple as compared to the approaches of traditional-step commutation and six-step with current feedback by experimental setting.

This thesis examines the application of Digital Signal Processing (DSP) techniques, and specifically Wavelets, to the field of automatic coin recognition. The aim is to utilise DSP techniques to exploit information that is contained within time domain signals representing coins, which can not be accessed by other means. Attention is also given to the power requirement of possible solutions, with a low power solution being a secondary aim, as the solutions are targeted for use in a line-powered payphone. An examination of existing coin recognition techniques is presented, for which an improved but basic DSP coin recognition scheme using peak and trough location, is achieved. This is then improved using more advanced DSP techniques to access previously unavailable information contained within the signals. The advanced DSP techniques are developed into an integrated framework for automatic coin recognition. The framework is used to identify a single Wavelet solution that supplies a DSP representation of a set of coins. The representations of different coin types exist within a region of n-dimensional Euclidean space, which the framework attempts to locate uniquely for each coin type. To enable the framework to operate successfully, a key feature presented is the resampling of the waveforms input into the framework, to normalise any temporal variations in the input data. The location of the single Wavelet for analysis can not be achieved analytically and so is obtained using a novel Data Mining solution to search a Wavelet dictionary for possible solutions. This thesis proves that utilisation of the time localisation properties of the Discrete Wavelet Transform is possible when taken together with a distance metric strategy. Appropriate results are presented to verify the performance of the Wavelet solutions provided by the framework, especially in respect of counteracting fraudulent coins in the recognition process. As an overall validation of the research solution, an emulation of the coin recognition system was produced that could validate coins in real time, this is also documented. Both the hardware and software components of the integrated framework which have been developed, are fully modular and hold significant potential for expansion and integration into newer, more powerful cost effective coin recognition systems.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / The traditional use of active RC-type filters as anti-aliasing filters in Pulse Code Modulation (PCM) systems is being replaced by the use of Digital Signal Processing (DSP) filters, especially when performance requirements are tight and when operation over a wide environmental temperature range is required. In order to keep systems more flexible, it is often desired to let the DSP filters run asynchronous to the PCM sample clock. This results in the PCM output signal being a sampling of the output of the DSP, which is itself a sampling of the input signal. In the analysis of the PCM data, the signal will have a periodic repeat of a previous sample, or a missing sample, depending on the relative sampling rates of the DSP and the PCM. This paper analyzes what effects can be expected in the analysis of the PCM data when these anomalies are present. Results are presented which allow the telemetry engineer to make an effective value judgment based on the type of filtering technology to be employed and on the desired system performance.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / The traditional use of active RC-type filters to provide anti-aliasing filters in Pulse Code Modulation (PCM) systems is being replaced by the use of Digital Signal Processing (DSP). This is especially true when performance requirements are stringent and require operation over a wide environmental temperature range. This paper describes the design of a multi channel digital filtering card that incorporates up to 100 unique digitally implemented cutoff frequencies. Any combination of these frequencies can be independently assigned to any of the input channels.

The design and implementation of the digital signal processing (DSP) based on a brushless DC (BLDC) motor sensorless driver with Sine PWM. Because of dispensable power consumption problems generated by closed-loop speed control methods with speed estimation signal feedback are adopted for improvement. In addition, current feedback is added to the driver for the sake of increasing efficiency. Then, sine wave closes 30¢X, 15¢X, and 8¢X to comparing the improvements for efficiency. Experimental results from a laboratory prototype are shown to verify the feasibility of the proposed scheme. The laboratory results show that current feedback and sine wave closed 8¢X have high efficiency.

This thesis presents novel techniques for the reduction of audio recordings and signal processing techniques as part of cough recognition. Evidence collected shows the reduction technique to be effective and the recognition techniques to give consistent performance across different patients. Cough is one of the commonest symptoms reported by patients to GPs. Despite this, it remains a significantly unmet medical need. At present, there exists no practical and validated technique for assessing the efficacy of therapies to treat cough on a large enough scale. Research that is presently undertaken requires fitting a patient with a recording system which will record their coughing and all other sound for a predefined period, usually 24 hours or less. This audio is then counted manually by trained cough counters to produce counts for each record which can be used as data for cough studies. Research in this field is relatively new, but a number of attempts have been made to automate this process. None so far have shown sufficient reliability or precision to be of sufficient use. The aim of this research is to analyse from the ground up signal processing techniques which can aid cough research. Specifically, the research will look into data minimisation techniques to improve the efficiency of manual counting techniques and recognition algorithmsThe research has produced a published record reduction system which can reduce 24 hour cough records down to around 10% of their original size without compromising the statistics of subsequent manual counts. Additionally, a review of signal processing techniques for cough recognition has produced a robust event detection technique and measurement techniques which have shown remarkable consistency between patients and conditions. Throughout the research a clear understanding of the limitations and possible solutions are pursued and reported on to aid further progress on what is a young and developing research field.

No description available.

The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E.g. mobile phones need to handle both second and third generation mobile telephony as well as Bluetooth, and will soon also support wireless LAN functionality, reception of digital audio and video broadcasting, etc. These developments have lead to an increased interest in software defined radio (SDR), i.e. radio devices that can be reconfigured via software. SDR would provide benefits such as low cost for multi-mode devices, reuse of the same hardware in different products, and increased product life time via software updates. One essential part of any software defined radio is a programmable baseband processor that is flexible enough to handle different types of modulation, different channel coding schemes, and different trade-offs between data rate and mobility. So far, programmable baseband solutions have mostly been used in high end systems such as mobile telephony base stations since the cost and power consumption have been considered too high for handheld terminals. In this work a new low power and low silicon area programmable baseband processor architecture aimed for multi-mode terminals is presented. The architecture is based on a customized DSP core and a number of hardware accelerators connected via a configurable network. The architecture offers a good tradeoff between flexibility and performance through an optimized instruction set, efficient hardware acceleration of carefully selected functions, low memory cost, and low control overhead. One main contribution of this work is a study of important issues in programmable baseband processing such as software-hardware partitioning, instruction level acceleration, low power design, and memory issues. Further contributions are a unique optimized instruction set architecture, a unique architecture for efficient integration of hardware accelerators in the processor, and mapping of complete baseband applications to the presented architecture. The architecture has been proven in a manufactured demonstrator chip for wireless LAN applications. Wireless LAN firmware has been developed and run on the chip at full speed. Silicon area and measured power consumption have proven to be similar to that of a non-programmable ASIC solution.