International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / A number of efforts at NASA's Johnson Space Center are exploring ways of improving operational efficiency and effectiveness of telemetry data distribution. An important component of this is the Real-Time Data System project in the Shuttle Mission Control Center. This project's telemetry system is based on a network of engineering workstations that acquire, distribute, analyze, and display the data. Telemetry data is acquired and partially processed through a commercial programmable telemetry processor. The data is then transferred into workstations where the remaining decommutation, conversion and calibration steps are performed. The results are sent over the network to applications operating within end user workstations. This complex distributed environment is managed by PILOT, an intelligent system that monitors data flow and process integrity with the goal of providing a very high level of availability requiring minimal human involvement. PILOT is a rule-based expert system that oversees the operation of the system. It interacts with agents that operate in the local environment of each workstation and advises the local agents of system status and configuration. This enables each local agent to manage its local environment and provides a resource to which it can come with issues that need a global view for resolution. PILOT is implemented using a commercially available real-time expert system shell and operates in a heterogeneous set of hardware platforms.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / A distributed architecture framework has been developed for NASA at Goddard Space Flight Center (GSFC) as the basis for developing an extended series of space mission support data systems. The architecture is designed to include both mission development and operations. It specifically addresses the problems of standardizing a framework for which commercial off-the-shelf (COTS) applications and infrastructure are expected to provide most of the components of the systems. The resulting distributed architecture is developed based on a combination of a layered architecture, and carefully selected open standards. The layering provides the needed flexibility in mission design to support the wide variability of mission requirements. The standards are selected to address the most important interfaces, while not over constraining the implementation options.

As transistor counts, power dissipation, and wire delays increase, the microprocessor industry is transitioning from chips containing large monolithic processors to multi-core architectures. The granularity of cores determines the mechanisms for branch prediction, instruction fetch and map, data supply, instruction execution, and completion. Accurate control flow prediction is essential for high performance processors with large instruction windows and high-bandwidth execution. This dissertation considers cores with very large granularity, such as TRIPS, as well as cores with extremely small granularity, such as TFlex, and explores control flow speculation issues in such processors. Both TRIPS and TFlex are distributed block-based architectures and require control speculation mechanisms that can work in a distributed environment while supporting efficient block-level prediction, misprediction detection, and recovery. This dissertation aims at providing efficient control flow prediction techniques for distributed block-based processors. First, we discuss simple exit predictors inspired by branch predictors and describe the design of the TRIPS prototype block predictor. Area and timing trade-offs in the predictor implementation are presented. We report the predictor misprediction rates from the prototype chip for the SPEC benchmark suite. Next, we look at the performance bottlenecks in the prototype predictor and present a detailed analysis of exit and target predictors using basic prediction components inspired from branch predictors. This study helps in understanding what types of predictors are effective for exit and target prediction. Using the results of our prediction analysis, we propose novel hardware techniques to improve the accuracy of block prediction. To understand whether exit prediction is inherently more difficult than branch prediction, we measure the correlation among branches in basic blocks and hyperblocks and examine the loss in correlation due to hyperblock construction. Finally, we propose block predictors for TFlex, a fully distributed architecture that uses composable lightweight processors. We describe various possible designs for distributed block predictors and a classification scheme for such predictors. We present results for predictors from each of the design points for distributed prediction. / text

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