In this thesis the focus was on the design, fabrication, and tests of the feeding networks individually and within an array system. The array feeding network is a corporate-fed type utilizing equal-split, stepped-multiple sections of the conventional Wilkinson power divider in microstrip form with a unique topology. The feeding network was specifically designed for a broadside relatively small linearly-polarized wideband UHF non-scanning array for directed power applications that uses an array radiator with a new volumetric ribcage dipole configuration. The array has a large impedance bandwidth and consistent front lobe gain over the wide frequency band. Theoretical and experimental results describing the performance of the array feeding network and the array are presented and discussed.

<p>This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical Engineering, Linköpings University, Sweden. </p><p>The purpose of the project is to design a wide frequency range programmable frequency divider used in a PLL circuit for ultra wide band system. 0.18 um tsmc CMOS technology is used in this project. </p><p>A brief introduction of PLL circuits and UWB specifications are given in the report and the circuit design issue is presented. Post-layout simulation results are shown in the later part of the report. </p><p>The focus of this project is to make the frequency divider work well in wide range and high speed. Therefore, how to shorten feedback circuits’ latency and how to reduce complexity of the circuits are the main problems. Logic gate merged technique is used to reduce transistor number and carefully drawing layout makes the circuit work well in post-layout simulation.</p>

The reflectarray has been considered as a suitable candidate to replace the conventional parabolic reflectors because of its high-gain, low profile, and beam reconfiguration capability. Beam scanning capability and multi-band operation of the microstrip reflectarray have been main research topics in the reflectarray design. Narrow bandwidth of the reflectarray is the main obstacle for the various uses of the reflectarray. The wideband antenna element with a large phase variation range and a linear phase response is one of the solutions to increase the narrow bandwidth of the reflectarray. A four beam scanning reflectarray has been developed. It is the offset-fed microstrip reflectarray that has been developed to emulate a cylindrical reflector. Unlike other microstrip reflectarrays which integrates phase tuning devices such as RF MEMS switches and another phase shifters to the reflectarray elements and control the reflected phase, the beam scanning capability of the reflectarray is implemented by a phased array feed antenna. This method can reduce the complexity of the design of the beam switching reflectarray. A simple method has been investigated to develop multi-band elements in this dissertation. In approach to increase the coverage of the operation bands, a six-band reflectarray has been developed with two layers. Each layer covers three frequency bands. A Butler matrix is one of the useful beamforming networks for a phased array antenna. A Double-Sided Parallel-Strip Line (DSPSL) is adapted for the feeding network of eight array elements. The DSPSL operate very well to feed the microstrip antenna array over the bandwidth to reduce the sidelobe level and a high gain. In another topic of a Butler matrix, a dual-band Butler matrix has been proposed for multi-band applications. A modified Butler matrix is used to reduce a size and a sidelobe level. The bandwidth of the microstrip antenna is inherently small. A broadband circularly polarized microstrip antenna with dual-offset feedlines is introduced in this dissertation. Aperture-coupled feed method is used to feed the stacked patch antennas and a slotcoupled directional coupler is used for the circularly polarized operation. The research presented in this dissertation suggests useful techniques for a beam scanning microstrip reflectarray, phased array antenna, and wideband antenna designs in the modern wireless communication systems.

This thesis proposes a new type of hydraulic valve: an adjustable-ratio flow divider. This valve attempts to split one input flow into two output flows in a predetermined ratio, independent of load pressure or total flow. The valve uses a two dimensional structure to form a two-stage valve with only one moving part; the pilot stage uses the spool s rotary position, and the main stage uses its linear position. This arrangement allows for a cheaper, simpler valve with smaller volumes (translating into faster response). The ratio of outlet flows can be set on the fly by the angular position of the spool, driven by a stepper motor or other low-power input. In order to evaluate the initial feasibility of the concept, steady state and dynamic models were developed and the effects of the physical parameters were studied. Two non-linear non-derivative multiobjective optimization strategies were used to determine the optimum parameters for a prototype. Finally, the prototype s performance was experimentally examined and appears to work as expected.

This thesis proposes a new type of hydraulic valve: an adjustable-ratio flow divider. This valve attempts to split one input flow into two output flows in a predetermined ratio, independent of load pressure or total flow. The valve uses a two dimensional structure to form a two-stage valve with only one moving part; the pilot stage uses the spool s rotary position, and the main stage uses its linear position. This arrangement allows for a cheaper, simpler valve with smaller volumes (translating into faster response). The ratio of outlet flows can be set on the fly by the angular position of the spool, driven by a stepper motor or other low-power input. In order to evaluate the initial feasibility of the concept, steady state and dynamic models were developed and the effects of the physical parameters were studied. Two non-linear non-derivative multiobjective optimization strategies were used to determine the optimum parameters for a prototype. Finally, the prototype s performance was experimentally examined and appears to work as expected.

Abstract The tremendous progress in all aspects of signal processing technology has naturally been accompanied by a corresponding development of arithmetic techniques to provide high-speed operations at reasonable complexity. In the past, many architectural design efforts have focused on maximizing performance for frequently executed simple arithmetic operations such as addition and multiplication while left other rarely used operations ignored. In this dissertation, we firstly propose two design approaches for 64-b carry-lookahead adders (CLA) using a two-phase clocking dynamic CMOS logic since fast adders are the key elements in many digital circuits. Secondly, we place emphasis on the inner product operation since it is one of the most frequently used mathematical operations in the computation of digital neural networks. A ratioed 3-2 compressor is also presented to resolve several physical design problems that are not fully considered or implemented in previous research works. Finally we propose several fast 64b/32b integer dividers because the integer division is unavoidable in many important signal-processing applications.

This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.

The work done in this thesis focuses on the design of a square-shaped 20-way metamaterial power divider which is fabricated in microstrip technology and operates at 1 GHz. The divider comprises 12 square-shaped left-handed unit cells and 13 square-shaped right-handed unit cells, and these unit cells have the same size and are placed in a checker-board tessellation, where the left-handed unit cells are connected only to right-handed unit cells and vice versa. The divider is based upon the infinite wavelength phenomenon in two-dimensions, and this means that the insertion phase between any two ports of the left-handed unit cell is equal, but with opposite sign, to that of the right-handed unit cell. The divider gives an equal-amplitude equal-phase power division from the central input port to the output ports which are located on a straight line on each side. Thus, it is convenient to integrate with, or interconnect to, other planar circuits in a system, such as power amplifier modules. The design concept can be extended to an N-way power divider, where N = 4n and n is an odd integer.

This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical Engineering, Linköpings University, Sweden. The purpose of the project is to design a wide frequency range programmable frequency divider used in a PLL circuit for ultra wide band system. 0.18 um tsmc CMOS technology is used in this project. A brief introduction of PLL circuits and UWB specifications are given in the report and the circuit design issue is presented. Post-layout simulation results are shown in the later part of the report. The focus of this project is to make the frequency divider work well in wide range and high speed. Therefore, how to shorten feedback circuits’ latency and how to reduce complexity of the circuits are the main problems. Logic gate merged technique is used to reduce transistor number and carefully drawing layout makes the circuit work well in post-layout simulation.

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