There is a lot of applications for DSPs (Digital Signal Processor) in the most rapidly growing areas in the industry right now as wireless communication along with audio and video products are getting more and more popular. In this report, a DSP, developed at the division of Computer Engineering at the University of Linköping, is optimized and verified. Register Forwarding was implemented on a general architecture level to avoiddata hazards that may arise when implementing instruction pipelining in a processor. The very common FFT algorithm is also optimized but on instruction setlevel. That means the algorithm is carefully analyzed to find operations that mayexecute in parallel and then create new instructions for these parallel operations.The optimization is concentrated on the butterfly operation as it is such a majorpart of the FFT computation. Comparing the accelerated butterfly with the unaccelerated gives an improvement of 30% in terms of clock cycles needed for thecomputation. In the report there are also some discussions about the benefits and drawbacksof changing from a hardware to a software stack, mostly in terms of interrupts andthe return instruction. Another important property of the processor is scalability. That is, it is possibleto attach extra peripherals to the core, which accelerates certain tasks. Aninterface towards these peripherals is developed along with two template designsthat may be used to develop other peripherals. After all these modifications, a new test bench is developed to verify the functionality.

Diploma thesis describes design and realization of hardware and software for controlling and regulation of the high-speed drive with BLDC motor, which will serve as a spindle for CNC milling machine. The thesis described in detail the schematic design and the design of printed circuit board of the power part, control part and power supply part of the three-phase transistor inverter controlled by DSP processor. It is also described in detail program of DSP processor for controlling and regulation of the BLDC motors, which the function is verified by the final measurements. The result of Diploma thesis is functional high-speed drive with BLDC motor.

Ce travail de thèse a pour objectifs l'observation et la commande des convertisseurs multi-niveaux et la commande des machines synchrones. Pour satisfaire le besoin des clients de l’entreprise GS Maintenance et pour des raisons de maintenance, une commande en courant de la machine synchrone est implémentée expérimentalement. L'accent est mis sur le démarrage de ce type de machines car durant ces phases de fonctionnement (basses vitesses), les forces électromotrices sont faibles pour assurer la commutation des thyristors de l'onduleur. Ensuite, l'entreprise a proposé à ses clients un convertisseur statique en moyenne tension afin de garder sa place dans la variation de vitesse. Dans ce cadre, une commande en tension moderne de la machine synchrone alimentée par un onduleur de tension est proposée et validée par des résultats de simulation. Compte tenu du fonctionnement en moyenne tension, les convertisseurs multi-niveaux ont été retenus par l’entreprise. Dans ce cadre, le convertisseur multicellulaire série est proposé dans ce travail et une commande directe basée sur la théorie des modes glissants et le principe de priorité est conçue pour assurer l'équilibrage des tensions flottantes du convertisseur. Cette commande a été généralisée pour un nombre quelconque de cellules du convertisseur et validée par des résultats de simulation pour un nombre de cellules égal à 7. Pour réduire le coût et l'encombrement du convertisseur, un observateur adaptatif des tensions flottantes est proposé en prenant en compte les états de commutation du convertisseur. Cet observateur est ensuite associé à la commande directe en boucle fermée. Un banc d'essai du convertisseur à 3 cellules est réalisé au sein de l’entreprise et l’ensemble « observateur + commande directe » est testé expérimentalement sur ce banc. / This PhD thesis aims to the observation and control of multilevel converters and the synchronous machines control. To satisfy the needs of GS Maintenance's customers and for maintenance reasons, a control strategy for a current fed self controlled synchronous machine is validated by experiments tests. The proposed strategy focus on a very low speed because the machine counter electromotive force is insufficient for inverter thyristors switching. Recently, the company proposed for its customers a power converter with medium voltage to keep its place in the speed variation. So, a modern voltage control of the synchronous machine fed by a voltage inverter is proposed and validated by simulation results. Medium voltage operation encouraged the company to choose the multi-level converter. Then, the flying capacitor converter is proposed in this work and a direct control based on the sliding mode theory and the priority principle is designed to guarantee the voltage balance. This control strategy has been generalized for any number of cells of the converter and validated by simulation results for a 7 cells converter. To reduce the cost and complexity of the converter, an adaptive observer floating voltages is proposed by taking into account the switching states of the converter. This observer is then associated with the direct control in closed loop. A test bench of a 3 cells converter is set up in the company. Experimental tests of « observer based direct control » are then conducted on this test bench.

Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed and pipelined solution to achieve a desired level of functionality and performance. Such a fixed processing solution is clearly not feasible for new algorithm evaluation or quick changes during field tests. A more flexible solution based on a high-performance soft-core processing architecture is proposed. To develop such a processing architecture, data and signal-flow characteristics of common radar signal processing algorithms are analysed. Each algorithm is broken down into signal processing and mathematical operations. The computational requirements are then evaluated using an abstract model of computation to determine the relative importance of each mathematical operation. Critical portions of the radar applications are identified for architecture selection and optimisation purposes. Built around these dominant operations, a soft-core architecture model that is better matched to the core computational requirements of a radar signal processor is proposed. The processor model is iteratively refined based on the previous synthesis as well as code profiling results. To automate this iterative process, a software development environment was designed. The software development environment enables rapid architectural design space exploration through the automatic generation of development tools (assembler, linker, code editor, cycle accurate emulator / simulator, programmer, and debugger) as well as platform independent VHDL code from an architecture description file. Together with the board specific HDL-based HAL files, the design files are synthesised using the vendor specific FPGA tools and practically verified on a custom high performance development board. Timing results, functional accuracy, resource usage, profiling and performance data are analysed and fed back into the architecture description file for further refinement. The results from this iterative design process yielded a unique transport-based pipelined architecture. The proposed architecture achieves high data throughput while providing the flexibility that a software-programmable device offers. The end user can thus write custom radar algorithms in software rather than going through a long and complex HDL-based design. The simplicity of this architecture enables high clock frequencies, deterministic response times, and makes it easy to understand. Furthermore, the architecture is scalable in performance and functionality for a variety of different streaming and burst-processing related applications. A comparison to the Texas Instruments C66x DSP core showed a decrease in clock cycles by a factor between 10.8 and 20.9 for the identical radar application on the proposed architecture over a range of typical operating parameters. Even with the limited clock speeds achievable on the FPGA technology, the proposed architecture exceeds the performance of the commercial high-end DSP processor. Further research is required on ASIC, SIMD and multi-core implementations as well as compiler technology for the proposed architecture. A custom ASIC implementation is expected to further improve the processing performance by factors between 10 and 27. / Dissertation (MEng)--University of Pretoria, 2013. / gm2014 / Electrical, Electronic and Computer Engineering / unrestricted

Conventional FMCW radar principle was implemented on Symeo 61 GHz LPR®-1DHP-R radar sensor system. There were few limitations of the FMCW implementation which needed to be removed. First, target separation in multi target environment was not possible for objects at same distance. For example, there are two targets, one is moving and one is static. When the moving target approaches the static target and becomes parallel to static target, which means they are at the same distance. At this point, the system is unable to distinguish between two targets. Second, high resolution in velocity measurement was needed. To overcome these limitations Range Doppler Signal Processing was proposed. For the implementation of the Range Doppler algorithm, first of all proof of concept is needed. Simulations are performed using MATLAB to simulate Range Doppler algorithm using raw data from the sensor. After successful simulation, prototype is developed using python. This also provides the real time visualization of Range Doppler signal processing along with peak detection with distance and velocity measurements. With the Range Doppler implementation, separation between static and moving target becomes possible. Later the algorithm is implemented on Texas Instrument DSP in C considering the resource limitations of the target hardware. To validate the Range Doppler implementation and to determine the measurements accuracy, multiple test setups are created. Two main local testing environments have been setup, linear unit and turntable. The system is tested on these environments for different velocities and distances along with multiple targets and on different surfaces. Furthermore, the system is tested at an industrial site for detecting the fluid speed, which is also possible with the Range Doppler implementation.

Digital Signal Processing(DSP) algorithms are widely implemented in real time systems.In fields such as digital music technology, many of these said algorithms areimplemented, often in combination, to achieve the desired functionality. When itcomes to implementation, DSP algorithms are performance critical as they havetight deadlines. In this thesis, performance optimization using Single InstructionMultiple Data(SIMD) vectorization technique is performed on the ARM Cortex-A15 architecture for six commonly used DSP algorithms; Gain, Mix, Gain and Mix,Complex Number Multiplication, Envelope Detection and Cascaded IIR Filter. Toensure optimal performance, the instructions should be scheduled with minimalpipeline stalls. This requires execution time to be measured with fine time granularity.First, a technique of accurately measuring the execution time using thecycle counter of the processor’s Performance Management Unit(PMU) along withsynchronization barriers is developed. It was found that the execution time measuredby using the operating system calls have high variations and very low timegranularity, whereas the cycle counter method was accurate and produced reliableresults. The cost associated with the cycle counter method is 75 clock cycles. Usingthis technique, the contribution by each SIMD instruction towards the executiontime is measured and is used to schedule the instructions. This thesis also presentsa guideline on how to schedule instructions which have data dependencies usingthe cycle counter timing execution time measurement technique, to ensure that thepipeline stalls are minimized. The algorithms are also modified, if needed, to favorvectorization and are implemented using ARM architecture specific SIMD instructions.These implementations are then compared to that which are automaticallyproduced by the compiler’s auto-vectorization feature. The execution times of theSIMD implementations was much lower compared to that produced by the compilerand the speedup ranged from 2.47 to 5.11. Also, the performance increaseis significant when the instructions are scheduled in an optimal way. This thesisconcludes that the auto-vectorized code does poorly for complex algorithms andproduces code with a lot of data dependencies causing pipeline stalls, even with fulloptimizations enabled. Using the guidelines presented in this thesis for schedulingthe instructions, the performance of the DSP algorithms have significant improvementscompared to their auto-vectorized counterparts. / Digitala signalbehandlingsalgoritmer(DSP) implementeras ofta i realtidssystem. Inomfält som exempelvis digital musikteknik används dessa algoritmer, ofta i olika kombinationer,för att ge önskad funktionalitet. Implementationen av DSP-algoritmerär prestandakritisk eftersom systemen ofta har små tidsmarginaler. I det härexamensarbetet genomförs prestandaoptimering med Single Instruction MultipleData(SIMD)-vektorisering på en ARM A15-arkitektur för 6 vanliga DSP-algoritmer;volym, mix, volym och mix, multiplikation av komplexa tal, amplituddetektering,och seriekopplade IIR-filter. Maximal optimering av algoritmerna kräver ocksåatt antalet pipeline stalls i processorn minimeras. För att kunna observera dettakrävs att exekveringstiden kan mätas med hög tidsupplösning. I det här examensarbeteutvecklas först en teknik för att mäta exekveringstiden med hjälp aven klockcykelräknare i processorns Performance Management Unit(PMU) tillsammansmed synkroniseringsbarriärer. Tidsmätning med hjälp av operativsystemsfunktionervisade sig ha sämre noggrannhet och tidsupplösning än metoden medatt räkna klockcykler, som gav tillförlitliga resultat. Den extra exekveringstidenför klockcykelräkning uppmättes till 75 klockcykler. Med den här tekniken är detmöjligt att mäta hur mycket varje SIMD-instruktion bidrar till den totala exekveringstiden.Examensarbete presenterar också en metod att ordna instruktioner somhar databeroenden sinsemellan med hjälp av ovanstående tidsmätningsmetod, såatt antalet pipeline stalls minimeras. I de fall det behövdes, skrevs koden till algoritmernaom för att bättre kunna utnyttja ARM-arkitekturens specifika SIMDinstruktioner.Dessa jämfördes sedan med resultaten från kompilatorns automatgenereradevektoriseringkod. Exekveringstiden för SIMD-implementationerna varsignifikant kortare än för de kompilatorgenererade och visade på en förbättring påmellan 2,47 och 5,11 gånger, mätt i exekveringstid. Resultaten visade också på entydlig förbättring när instruktionerna exekveras i en optimal ordning. Resultatenvisar att automatgenererad vektorisering presterar sämre för komplexa algoritmeroch producerar maskinkod med signifikanta databeroenden som orsakar pipelinestalls, även med optimeringsflaggor påslagna. Med hjälp av metoder presenteradei det här examensarbete kan prestandan i DSP-algoritmer förbättras betydligt ijämförelse med automatgenererad vektorisering.

Information is often stored and transmitted through electrical signals. This information may need refinement, which may be done by processing and altering the electrical signals, in which it is transmitted. When refining a signal, a frequency selective filter is often used. It can be implemented through digital signal processing (DSP). DSP is a concept where signals are refined using a digital compute system. Digital systems are designed to replace their analog counterpart, mitigating their flaws in scalability, complexity and cost. A DSP system is typically implemented using software on a small computer, while analog systems are implemented through various electronic components. The objective of this project is to design a DSP system that filters analog input data using automatically synthesised filters from user-defined input specifications. The DSP system is implemented using a microcontroller. The system designed the filters and found the filter coefficients. It then uses analog to digital converter (ADC) to sample an input signal and applies the filter. Lastly, it uses the digital to analog converter (DAC) to reconstruct a filtered, analog result. A user interface is not designed for the system, and only a limited number of filters are implemented. However, the system is successful in designing filters and finding their coefficients.

The division of computer engineering at Linköping’s university is currentlydeveloping an innovative parallel DSP processor architecture called ePUMA. Onepossible future purpose of the ePUMA that has been thought of is to implement itin base stations for mobile communication. In order to investigate the performanceand potential of the ePUMA as a processing unit in base stations, a model of theLTE physical layer uplink receiving chain has been simulated in Matlab and thenpartially mapped onto the ePUMA processor.The project work included research and understanding of the LTE standard andsimulating the uplink processing chain in Matlab for a transmission bandwidth of5 MHz. Major tasks of the DSP implementation included the development of a300-point FFT algorithm and a channel equalization algorithm for the SIMD unitsof the ePUMA platform. This thesis provides the reader with an introduction tothe LTE standard as well as an introduction to the ePUMA processor. Furthermore,it can serve as a guidance to develop mixed point radix FFTs in general orthe 300 point FFT in specific and can help with a basic understanding of channelequalization. The work of the thesis included the whole developing chain from understandingthe algorithms, simplifying and mapping them onto a DSP platform,and testing and verification of the results.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / The traditional use of active RC-type filters as anti-aliasing filters in Pulse Code Modulation (PCM) systems is being replaced by the use of Digital Signal Processing (DSP) filters, especially when performance requirements are tight and when operation over a wide environmental temperature range is required. In order to keep systems more flexible, it is often desired to let the DSP filters run asynchronous to the PCM sample clock. This results in the PCM output signal being a sampling of the output of the DSP, which is itself a sampling of the input signal. In the analysis of the PCM data, the signal will have a periodic repeat of a previous sample, or a missing sample, depending on the relative sampling rates of the DSP and the PCM. This paper analyzes what effects can be expected in the analysis of the PCM data when these anomalies are present. Results are presented which allow the telemetry engineer to make an effective value judgment based on the type of filtering technology to be employed and on the desired system performance.

An increasing adoption of digital signal processing (DSP) in optical fiber telecommunication has brought to the fore several interesting DSP enabled modulation formats. One such format is orthogonal frequency division multiplexing (OFDM), which has seen great success in wireless and wired RF applications, and is being actively investigated by several research groups for use in optical fiber telecom. In this dissertation, I present three implementations of OFDM for elastic optical networking and distributed network control. The first is a field programmable gate array (FPGA) based real-time implementation of a version of OFDM conventionally known as intensity modulation and direct detection (IMDD) OFDM. I experimentally demonstrate the ability of this transmission system to dynamically adjust bandwidth and modulation format to meet networking constraints in an automated manner. To the best of my knowledge, this is the first real-time software defined networking (SDN) based control of an OFDM system. In the second OFDM implementation, I experimentally demonstrate a novel OFDM transmission scheme that supports both direct detection and coherent detection receivers simultaneously using the same OFDM transmitter. This interchangeable receiver solution enables a trade-off between bit rate and equipment cost in network deployment and upgrades. I show that the proposed transmission scheme can provide a receiver sensitivity improvement of up to 1.73 dB as compared to IMDD OFDM. I also present two novel polarization analyzer based detection schemes, and study their performance using experiment and simulation. In the third implementation, I present an OFDM pilot-tone based scheme for distributed network control. The first instance of an SDN-based OFDM elastic optical network with pilot-tone assisted distributed control is demonstrated. An improvement in spectral efficiency and a fast reconfiguration time of 30 ms have been achieved in this experiment. Finally, I experimentally demonstrate optical re-timing of a 10.7 Gb/s data stream utilizing the property of bound soliton pairs (or "soliton molecules") to relax to an equilibrium temporal separation after propagation through a nonlinear dispersion alternating fiber span. Pulses offset up to 16 ps from bit center are successfully re-timed. The optical re-timing scheme studied here is a good example of signal processing in the optical domain and such a technique can overcome the bandwidth bottleneck present in DSP. An enhanced version of this re-timing scheme is analyzed using numerical simulations.