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<p>In this master thesis, control algoritms using arm side sensors are investigated for an industrial robot. The sensors can be position encoders placed after the gearbox and accelerometers on the robot arms. Control strategies are discussed and evaluated for different models of the robot, after which chosen strategies are applied to a realistic model. </p><p>Control algoritms using arm side sensors (LQ, dual-loop and PD-PID) are compared to a PID-controller that only uses measurements of motor position for feedback control. The comparison are done with respect to disturbance rejection, oscillation damping, robustness and tracking performance of a reference trajectory. </p><p>Results from tests with the realistic robot modell shows that disturbance rejection was improved a factor 2 to 5 while tracking performance was improved a factor 4 to 5 according to maximum deviation from the reference path. At the same time good re-sults are achieved regarding oscillation damping and robustness.</p>

In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components. Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach. The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.

In this master thesis, control algoritms using arm side sensors are investigated for an industrial robot. The sensors can be position encoders placed after the gearbox and accelerometers on the robot arms. Control strategies are discussed and evaluated for different models of the robot, after which chosen strategies are applied to a realistic model. Control algoritms using arm side sensors (LQ, dual-loop and PD-PID) are compared to a PID-controller that only uses measurements of motor position for feedback control. The comparison are done with respect to disturbance rejection, oscillation damping, robustness and tracking performance of a reference trajectory. Results from tests with the realistic robot modell shows that disturbance rejection was improved a factor 2 to 5 while tracking performance was improved a factor 4 to 5 according to maximum deviation from the reference path. At the same time good re-sults are achieved regarding oscillation damping and robustness.

This dissertation demonstrates that a magnetic-levitation (maglev) stage has the capabilities to control movements and reject vibration simultaneously. The mathematical model and vibration control scheme with a 6-degree-of-freedom (6-DOF) maglev stage for nanoscale positioning are developed for disturbance rejection. The derived full nonlinear dynamic equation of motions (EOMs) of the maglev stage include translational and rotational motions with differential kinematics. The derived EOMs and the magnetic forces are linearized to design a multivariable controller, a Linear Quadratic Gaussian with Loop Transfer Recovery (LQG/LTR), for vibration disturbance rejection in a multi-input multi-output (MIMO) system. For a more accurate model, the dynamics of an optical table with a pneumatic passive isolation system is also considered. The model of the maglev stage with the optical table is validated by experiments. Dual-loop controllers are designed to minimize the influence of the vibration disturbance between the moving platen and the optical table in the x-, y-, and z-axes motions. The inner-loop compensator regulates the velocity to reject vibration disturbance and the outer-loop compensator tracks positioning commands. When the vibration disturbances of 10 to 100 Hz are applied, the vibration-reduction ratios are about 30 to 65 percent in horizontal motion and 20 to 45 percent in vertical motion. In addition, the vibration disturbances of 45.45 Hz are attenuated by about 4 to 40 percent in angular motions. The vibration control schemes are effective in not only translational but rotational motions. In step responses, the vibration control schemes reduce the wandering range in the travel from the origin to another location. Positioning and tracking accuracies with the vibration controller are better than those without the vibration controller. In summary, these dual-loop control schemes with velocity feedback control improved the nanopositioning and vibration/disturbance rejection capabilities of a maglev system.

<p>In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components.</p><p>Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach.</p><p>The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.</p>

Σκοπός αυτής της διπλωματικής εργασίας είναι η σχεδίαση και υλοποίηση συνθέτη συχνοτήτων διπλού βρόχου σε συχνότητες 3-6 GHz για ασύρματες εφαρμογές UWB και HiperLAN2. Ο συνθέτης συχνοτήτων σχεδιάστηκε με διακριτά στοιχεία, χρησιμοποιώντας την αρχιτεκτονική του βρόχου κλειδωμένης φάσης (PLL) και λειτουργεί με 2 τρόπους, είτε παράγοντας σήματα συχνότητας από 3168 MHz έως 6336 MHz με βήμα συχνότητας 528 MHz, είτε παράγοντας σήματα συχνότητας από 4800 MHz έως 5000 MHz με βήμα συχνότητας 10 MHz. Παρά το γεγονός ότι η αρχιτεκτονική διπλού βρόχου έχει αντικατασταθεί από την αρχιτεκτονική fractional-N για λόγους κατανάλωσης και κόστους, πλεονεκτεί σε εφαρμογές ασύρματων δικτύων με αυστηρές απαιτήσεις ως προς την ακρίβεια της παραγόμενης συχνότητας και το θόρυβο φάσης. Η απλή αρχιτεκτονική integer-N δεν είναι επαρκής για την εκπλήρωση των απαιτήσεων σε μεγάλη ευκρίνεια και μικρό θόρυβο φάσης, λόγω του περιορισμένου εύρους ζώνης του βρόχου και του μεγάλου λόγου διαίρεσης Ν του διαιρέτη συχνοτήτων του βρόχου. Με την αρχιτεκτονική διπλού βρόχου χρησιμοποιούμε δυο βρόχους για να αμβλύνουμε την αντίθεση μεταξύ των παραπάνω παραγόντων, οι οποίοι καθορίζουν τη συμπεριφορά και την απόδοση του συνθέτη συχνοτήτων. Με τη χρήση διακριτών στοιχείων για την υλοποίηση των δυο βρόχων αποσκοπούμε σε καλύτερη συμπεριφορά του συστήματος ως προς το θόρυβο φάσης, καθώς και σε πιο ευέλικτο σχεδιασμό, που δίνει τη δυνατότητα μείωσης της ισχύος των ανεπιθύμητων συνιστωσών του σήματος αναφοράς στην έξοδο του συστήματος. / The purpose of this diploma thesis is the design and implementation of a dual loop frequency synthesizer, operating at frequencies ranging from 3 to 6 GHz, for wireless network applications, using UWB and HiperLAN2 standards. The frequency synthesizer’s design was based on dual loop synthesizer architecture and the use of modular components. The designed frequency synthesizer is able to function in 2 modes, by either producing signals in the frequency range of 3168 MHz - 6336 MHz with 528 MHz resolution, or signals in the frequency range of 4800 MHz - 5000 MHz with 10 MHz resolution. Although the dual loop architecture has long been replaced by the fractional-N architecture due to increased cost and power consumption, it is more suitable in wireless network applications demanding high precision in frequency synthesis and low phase noise. The integer-N architecture fails to satisfy these demands, due to the limited loop bandwidth and the large division ratio Ν of the loop’s frequency divider. The dual loop architecture uses two loops in order to alleviate the opposing demands in high frequency synthesis accuracy and low phase noise, which determine the behavior and performance of the frequency synthesizer. The use of modular components aims at better phase noise performance, as well as a more flexible design, thus resulting in a more efficient power dissipation of the spurious components of the reference signal at the synthesizer output.

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