In this thesis, the baseband signal processing and hardware implementation of the Digital Video Broadcasting - Handheld (DVB-H) are investigated. DVB-H is an emerging and promising wireless communication system and is based on the Orthogonal Frequency Division Multiplexing (OFDM) scheme. The algorithms for baseband signal processing include timing synchronization, frequency offset compensation, channel estimation, and scatter pilot detection. The developed algorithms are verified using Matlab program to meet performance requirements. Then, the algorithms are implemented using Verilog hardware description language (HDL), which is downloaded to Xilinx FPGA (Field Programmable Gate Array) for system verification. The selected algorithms for baseband signal processing have to meet the both the requirements of system performance and low complexity.

Darmstadt, Techn. Universiẗat, Diss., 2003. / Dateien im PDF-Format.

<p>Vid sändning av digital television är det möjligt att utöver ljud och bild även sända och erbjuda olika typer av tjänster och applikationer till mottagare. Vid utveckling av applikationer för digital television kan man välja att utveckla i antingen DVB-J (som är en bantad variant av Java för exekvering i Set-Top-Boxar) eller i DVB-HTML (som till stor del överensstämmer med XHTML). Syftet med detta arbete är att utreda hur DVB-J och DVB-HTML kan kombineras i en och samma applikation och hur interoperabilitet kan uppnås mellan DVB-J och DVB-HTML.</p>

In this dissertation we deal with methods of minimizing block artefacts in digital terrestrial TV broadcasting. These artefacts are caused by compressions based on the cosine transformation (JPEG, MPEG2 I-Frames). The aim of this work is therefore to create a DVB-J application the main function of which would be to minimize block artefacts in natural images transmitted by DVB-T. That is why we first inquire into the technology of DVB digital transmission and MHP platform which provides the function and the running of interactive applications. Next, we define differences between Java and JavaTV languages and describe the way they develop, simulate and start DVB-J applications. In the following part of this work, we analyze methods that can be used to detect and minimize block artefacts. Further on, we describe the design of an adaptive filter which minimizes block artefacts (hereinafter just ´MHP-MBA´). The major result of the entire work is an MHP-Deblocking application that in itself implements a newly created MHP-MBA deblocking filter as well as a filter from video kodek H.263. In the final part we concern ourselves with testing this application on a genuine set-top-box in DVB-T broadcasting.

ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Orthogonal frequency division multiplexing (OFDM) is a new technique for data transmission. Conforming to the final draft of OFDM-based DVB-T (ETSI EN 300 744 V1.6.1), which is intended for digital terrestrial television broadcasting, a DVB-T baseband system is designed. The system performance is simulated in MATLAB using Simulink. Then it is implemented on Field Programmable Gate Array (FPGA) with the help of System Generator software. The result shows that OFDM is robust against multipath effect and convenient for implementation as well, thus owning a quite promising future.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near- Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratied wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratied in 2005.<p> In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of congurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that veries the parity-check equations of the LDPC codes. Furthermore, a special characteristic of ve of the codes dened in the DVB-S2 standard and their in uence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratified in 2005. In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standard and their influence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near- Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratied wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratied in 2005.<p> In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of congurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that veries the parity-check equations of the LDPC codes. Furthermore, a special characteristic of ve of the codes dened in the DVB-S2 standard and their in uence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratified in 2005. In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standard and their influence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

This thesis includes two topics. The first topic is a 868/915 MHz band ZigBee physical layer design. The second topic is a synchroniza- -tion design of DVB-T demodulators. The first topic includes simulations and a hardware design. This chip is a physical layer design for IEEE Std 802.15.4 standard applications, including both a transmitter and a receiver for 868/915 MHz band. The measurement of the maximum power is about 144 &#x00B5;W at 2.4 MHz. This chip is proved to be compliant with a low power consumption requirement. The second topic mainly includes an introduction of the DVZB-T transmitter, equivalent channel model, a demodulation design of the receiver and simulations. The algorithms of the receiver include symbol timing synchronization, frequency offset estimation and its compensation and scattered pilots synchronization.