High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.05𝑚𝑚2 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net 𝐹𝑂𝑀𝐴 of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is > 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator.

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception.

Thesis (M.Eng.), Memorial University of Newfoundland, 2000. / Bibliography: leaves 105-109.

Thesis--M. Sc.(Eng.), University of Hong Kong. / Mimeographed.

No description available.

The power transfer capability of long high voltage transmission lines is often limited by the inductive reactance of the transmission line. Series compensation is in some instances employed to lower the inductive reactance of the transmission line which increases the transmission line power transfer capability. Numerous methods have been employed to provide series compensation of a transmission line. One such method is to use a thyristor controlled series capacitor (TCSC). A thyristor controlled senes capacitor (TCSC) belongs to the flexible altemating CUlTent transmission systems (FACTS) family of devices. It is a variable capacitive and inductive reactance device that can be used to provide series compensation in high voltage transmission lines. One of the significant advantages that a TCSC has over other series compensation devices is that the TCSC's reactance is instantaneously and continuously variable. This means that the TCSC can be used not only to provide series compensation but can also be used to enhance the stability of the power system. However accurate control of the TCSC is challenging due to its highly non-linear variable reactance characteristic. The TCSC consists of back to back thyristors that control the reactance of the TCSC. By changing the trigger angle of these back to back thyristors it is possible to vary the reactance of the TCSC. The reactance characteristic becomes highly non linear at higher levels of compensation; at such operating points the trigger angle of the thyristors needs to be accurately controlled to avoid small variations in the thyristor trigger angle causing significant variation in the reactance of the TCSC. Literature has shown that there is an acceptable limit to the resolution of the thyristor trigger angle based on the parameters of the components used in the TCSC. If a controller is developed to meet this acceptable level of thyristor trigger angle resolution, then the operation of the TCSC will also be acceptable and its operation will not result in unwanted fluctuations in the transmission line variables. This thesis details the development of such a controller for use in a laboratory-scale TCSC. The thesis then goes on to present the practical results obtained from laboratory experiments on the laboratory-scale TCSC with the TCSC triggering controller being used to control the operation of the laboratory-scale TCSC. For purposes of comparison and benchmarking, a detailed simulation model of the laboratory-scale TCSC is developed to take into account the non-ideal properties of the components used in make-up of the laboratory-scale TCSC since the theoretical model is derived assuming ideal conditions. The detailed simulation model is also used to aid in the redesign the power circuit of the laboratory-scale TCSC in an attempt to improve the perfonnance of the laboratory-scale TCSC by obtaining better agreement between the theoretical and practical results. The redesigned laboratory-scale TCSC is used to obtain practical results to COnfill11 the findings of the simulation studies. Finally, the TCSC triggering controller is tested using a real time digital simulator (RTDS). The simulation model developed on the RTDS consisted of a two area, four generator power, with the TCSC connected between the two areas. The RTDS simulation model is used to study the ability of the TCSC to damp inter-area mode oscillations and hence the RTDS simulation model incorporated a power oscillation controller. The input of TCSC triggering controller was "connected" to the power oscillation damping controller and the output of the TCSC triggering controller was "connected" to the thyristors of the TCSC. / Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2007.

No description available.

Thesis (PhD)--University of South Australia, 1995

Thesis (PhD)--University of South Australia, 1995

Thesis (M.S.)--University of Texas at Dallas, 2008. / Includes vita. Includes bibliographical references (leaves 124-133)