Thesis (Ph. D. in Teaching and Learning)--Vanderbilt University, Aug. 2006. / Title from title screen. Includes bibliographical references.

Ph.D. / Please refer to full text to view abstract

In 1854 Cayley proposed an interesting sequence 1,1,3,13,75,541,... in connection with analytical forms called trees. Since then there has been various combinatorial interpretations of the sequence. The sequence has been interpreted as the number of preferential arrangements of members of a set with n elements. Alternatively the sequence has been interpreted as the number of ordered partitions; the outcomes in races in which ties are allowed or geometrically the number of vertices, edges and faces of simplicial objects. An interesting application of the sequence is found in combination locks. The idea of a preferential arrangement has been extended to a wider combinatorial object called barred preferential arrangement with multiple bars. In this thesis we study barred preferential arrangements combinatorially with application to resistance of certain electrical circuits. In the process we derive some results on cyclic properties of the last digit of the number of barred preferential arrangements. An algorithm in python has been developed to find the number of barred preferential arrangements.

This thesis deals with the modelling and circuit simulation problems of nonlinear electronic devices. Emphasis has been aimed at MOSFET devices. A Piecewise Linear (PWL) modelling scheme has been proposed for a general four-terminal nonlinear charge device. The charge functions are all nonlinear and are approximated by PWL functions. If analytical expressions for the nonlinear functions are not available, PWL function approximations can be built from a data table in which discrete data points are recorded. In the time domain, the critical-damping-adjustment (CDA ) scheme is used as the integration rule in the discretization of dynamic charge devices. Piecewise linear modelling combined with the CDA integration scheme gives a fast yet adequately accurate simulation algorithm. The algorithm is based on linear analysis because the entire circuit becomes linear with PWL modelling of nonlinear elements. In order to avoid an iterative solution, PWL region extrapolation is permitted when the circuit solution switches PWL regions. The extrapolation approximation will generate an overshoot error in the solution vector. However, with caution in the selection of the integration step size, the error can be limited to an acceptable range. Two types of MOSFETs have been modelled and simulated with the algorithm introduced in this thesis, and satisfactory results have been obtained as compared to Newton's iteration solutions. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

M.Ing. / Please refer to full text to view abstract

No description available.

This paper presents a method of simulating various noise sources in a Weapons Fire Simulator System which has been modeled as an Optical Communication Channel. This Weapons Fire Simulator System is composed of laser transmitters mounted on weapons that fire blank cartridges, and laser receivers mounted on targets. The laser transmitter sends out 'kill' beam pulses to the target whenever blank cartridges are fired. Detection of these pulses at the target signifies a 'hit'. The entire system along with the optical communication channel is simulated in a general purpose computer program called SCEPTRE. This analysis package is an efficient means of modeling the communication channel characteristics and determining signal to noise ratios as functions of various electrical and physical parameters. Also the SCEPTRE program is a versatile tool for circuit noise calculations. The main advantage is a single SCEPTRE run computes the total noise output from a large number of noise sources distributed throughout the circuit.

An active power factor correction circuit with controlled on-time is proposed. The circuit has a simpler control scheme than the power bc10r correction circuit with hysteresis control, and yet is able to attain high power factor. A very important aspect of this work was the formulation of the design guidelines for the input filter for the power factor correction circuit. Conventional methods of filter design may introduce an unwanted phase shift between the input voltage and current, thereby degrading the power factor. The cause of this phase shift is explained and based upon it, the design guidelines for the input filter are established. The FFT is used to more accurately define the input filter attenuation requirement. A comparison is made between power factor correction circuit with controlled on-time and the power factor correction circuit with hysteresis control (with input filter for both of them) on the basis of their minimum weight. A regulated 100 W, 120 VAC input and 300 V output power factor correction circuit was implemented on a breadboard. Ridley's small signal switch model [10] for the power factor correction circuit with hysteresis control is successful1y app1ied to this control scheme to close the loop. / Master of Science

Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit layout editor which enables the user to create circuit layouts and select portions of the circuit for parasitic computation. (2) XT Mesh A two and three dimensional fully automatic mesh generator. The mesh generator combines the quadrant/octant subdivision method and Watson's algorithm in a four step process. Initial triangulations are created and cell compatibility is ensured using an alternating initial mesh scheme. This method produces substantial time savings by avoiding the use of data tree structures and stringent cell size rules. (3) XT Field Solver A two and three dimensional finite element quasi-TEM solver which calculates the capacitance and inductance between circuit metalizations. / Master of Science

A thorough investigation or existing publications was conducted to determine the etfeet on phase-locked loop operation of the pass band or the low-pass filter in the loop. From the findings, it was concluded that when the loop was out of lock, the pass band of the low-pass filter should be wide; however, when the loop was locked, the pass band of the low-pass filter should be narrow. The transient analysis or the loop demonstrated that it was desirable to have a wide pass band for the filter in order to minimize the lock-in time of the loop. An analog simulation of the loop verified the transient analysis. The loop simulation required the synthesis of the low-pass filter with operational building blocks in such a way that the pass band could be controlled as potentiometer settings. The desirability of a variable pass band and low-pass filter was established. The condition that the filter must be able to sense when the loop was either locked or out of lock and adjust its pass band accordingly was set as a prerequisite for the design of a filter. A filter was built and tested which could meet the above conditions. The limited range of the filter left a lot to be desired; however, the feasibility of the approach was demonstrated. / Master of Science