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No description available.

No description available.

Thesis (M.S.)--Ohio University, November, 1986. / Title from PDF t.p.

Thesis (M.Sc.)--University of Hong Kong, 1964. / Also available in print.

Thesis (SC. D.)--University of Michigan, 1935. / "Reprint from Electrical engineering ... March 1937." Includes bibliographical references (p. 8).

Thesis (M.S.)--University of Wisconsin--Madison, 1967. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Thesis (Ph. D.)--Columbia University, 1940. / Vita. Lithoprinted.

Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power product(SPP). 32-bit CMOS adders are used as representative circuits to investigate a method of reducing the SPP. The purpose of this thesis is to show that sizing gates according to fan-out and removing buffer drivers can reduce the SPP. This thesis presents a method for sizing gates in large fan-out parallel prefix circuits to reduce the SPP and compares it to other methods. Three different parallel prefix adders are used to compare propagation delay and SPP. The first adder uses the depth-optimal prefix circuit. The second adder is based on Wei, Thompson, and Chen's time-optimal adder. The third adder uses a recursive doubling formation where all cells have minimum transistor width dimensions. The component cells in the adders are static CMOS as described by Brent and Kung. For all circuits, the smallest propagation delay occurs when the highest voltage supply is applied. The smallest SPP occurs when the lowest voltage supply is applied, but with the lowest performance. The Recursive Doubling Adder always has the lowest propagation delay for a particular set of parameters. However, its SPP is nearly equal to the Brent-Kung Adders and lower than Wei's Adder. The power-frequency analysis reveals that a decrease in Vt causes higher power consumption due to leakage. / Graduation date: 1999

The improved accuracy of Time Domain Reflection and Transmission (TDR/T) measurements made possible by the calibration process known as Time Domain Network Analysis (TDNA) is applied to the problem of characterization and modeling of electronic interconnect and packaging structures. TDNA uses measurements of known and partially known calibration standards to characterize the measurement system allowing for the correction of the raw measurements of an unknown network to eliminate the effects of system non-idealities and resulting in a significant improvement of the measurement quality. The correction process is shown to be analogous to the well established Frequency Domain Vector Network Analyzer calibrations and to have the same capabilities for high precision metrology applications. Methods are developed to extract electrical circuit models from time domain measurements of lossless, nonuniform, multiconductor transmission lines for two broad classes of structures. Although unique solutions are not feasible for general structures that scatter the propagating wave-front, approximate solutions have been identified using the assumption of a single velocity wave-front, the case for homogeneous media. For structures with identical lines, such as a parallel line bus structure, the propagation behavior (eigenvector matrix) is determined only by the number of conductors, N, and is therefore known a priori for the entire structure allowing decoupling of the system into N orthogonal nonuniform transmission lines. Circuit models have been developed for these decoupled nonuniform lines as well as for the equal modal velocity assumption which relies on a matrix impedance profile to fully describe the system. The implications of non-ideal grounding of interconnection circuits is explored. Traditional lumped element methods for modeling these effects are examined and typical examples where distributed circuit models are necessary to adequately describe the system are identified. Techniques for examining power-planes and substrate connections in integrated circuits and integrated circuit packages using the distributed ground model are presented. Novel circuit design methods to circumvent the limitations imposed by non-ideal grounds and nonzero length transmission structures are also proposed. / Graduation date: 1994