Reducing circuit complexity to minimize design turnaround time and maximize chip area utilization is the most evident problem in dealing with VLSI layout. Three suggestions have been recommended to reduce circuit complexity. They are using regular modules as design targets, using hierarchical top-down design as a design methodology, and using CAD as a design tool. These three suggestions are the basis of this dissertation project. In this dissertation, three silicon compilers were implemented which take an universal AHPL circuit description as an input and automatically translate it into SLA (Storage Logic Array), PPLA (Path Programmable Logic Array), and ULA (Uncommitted Logic Array) chip layout. The goal is to study different layout algorithms and to derive better algorithms for alternative VLSI structures. In order to make a precise chip area comparison of these three silicon compilers, real SLA and ULA circuits have been designed. Four typical AHPL descriptions of different circuits or varying complexity were chosen as comparison examples. The result shows that the SLA layout requires least area for circuit realization generally. The PPLA approach is the worst one for large scale circuit realization, while the ULA lies in between.

by C.Y. Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [147]-[148]

by Yeung, Lap Kun. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 96-98). / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgements --- p.iv / Table of Contents --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Emergence of LTCC Technology --- p.1 / Chapter 1.2 --- Overview of the Work --- p.2 / Chapter 1.3 --- Original Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Fundamentals of Partial Element Equivalent Circuit Modeling --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- PEEC Formulation --- p.6 / Chapter 2.2.1 --- Mixed potential integral equation --- p.6 / Chapter 2.2.2 --- Current discretization --- p.7 / Chapter 2.2.3 --- Charge discretization --- p.8 / Chapter 2.2.4 --- Galerkin matching --- p.9 / Chapter 2.3 --- Partial Inductance --- p.11 / Chapter 2.4 --- Partial Capacitance --- p.12 / Chapter 2.5 --- Meshing Scheme and Circuit Interpretation --- p.13 / Chapter 2.6 --- Summary --- p.15 / Chapter 3 --- PEEC Modeling of LTCC RF Circuits using Thin-film Approximation --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- A Simple LTCC Band-pass Filter --- p.17 / Chapter 3.3 --- Discretization Scheme --- p.18 / Chapter 3.4 --- Quasi-static Green's Functions --- p.21 / Chapter 3.4.1 --- Free-space Green's function --- p.21 / Chapter 3.4.2 --- System with a single ground plane --- p.22 / Chapter 3.4.3 --- System with two ground planes --- p.25 / Chapter 3.5 --- Complex-Image Analysis --- p.25 / Chapter 3.6 --- Partial Inductance --- p.31 / Chapter 3.6.1 --- Strip-to-strip inductance --- p.31 / Chapter 3.6.2 --- System with one or more ground planes --- p.33 / Chapter 3.7 --- Partial Capacitance --- p.34 / Chapter 3.8 --- Numerical and Experimental Results --- p.37 / Chapter 3.9 --- Summary --- p.40 / Chapter 4 --- PEEC Modeling of LTCC RF Circuits using Thin-film Approximation (Via-hole Modeling) --- p.41 / Chapter 4.1 --- Introduction --- p.41 / Chapter 4.2 --- Via-hole Modeling --- p.42 / Chapter 4.2.1 --- Discretization scheme --- p.42 / Chapter 4.2.2 --- Inductance formulae --- p.43 / Chapter 4.2.3 --- Empirical formula --- p.46 / Chapter 4.2.4 --- Edge-effect compensation --- p.48 / Chapter 4.3 --- Numerical and Experimental Results --- p.49 / Chapter 4.4 --- Summary --- p.51 / Chapter 5 --- An Efficient PEEC Algorithm for Modeling of LTCC RF Circuits with Finite Metal Strip Thickness --- p.53 / Chapter 5.1 --- Introduction --- p.53 / Chapter 5.2 --- PEEC Modeling using Thin-film Approximation --- p.54 / Chapter 5.3 --- PEEC Modeling with Finite Metal Thickness --- p.55 / Chapter 5.4 --- Edge-effect Compensation in Inductance Calculation --- p.57 / Chapter 5.5 --- Numerical and Experimental Results --- p.61 / Chapter 5.6 --- Summary --- p.65 / Chapter 6 --- A Compact Second-order LTCC Band-pass Filter with Two Finite Transmission Zeros --- p.66 / Chapter 6.1 --- Introduction --- p.66 / Chapter 6.2 --- Features of the Filter --- p.67 / Chapter 6.3 --- Design Theory --- p.68 / Chapter 6.4 --- LTCC Filter Implementation --- p.70 / Chapter 6.4.1 --- Circuit model --- p.70 / Chapter 6.4.2 --- Physical layout --- p.73 / Chapter 6.5 --- Experimental Results --- p.75 / Chapter 6.6 --- Summary --- p.77 / Chapter 7 --- Concluding Remarks --- p.79 / Chapter 7.1 --- PEEC Modeling --- p.79 / Chapter 7.2 --- Limitations of the Algorithm --- p.80 / Chapter 7.3 --- Further Improvements --- p.81 / Appendix --- p.82 / References --- p.96 / Author's Publications --- p.98

Photocopy of typescript. / Digitized by Kansas Correctional Industries

Thesis. 1976. B.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / Microfiche copy available in Archives and Engineering. / by Gustav Laub III. / B.S.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Lennox P. John Hoyte. / M.S.

Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped with the ability to sense, compute, communicate with each other and perform tasks in a coordinated manner, security and power management are among the most critical challenges. Physically unclonable function (PUF) emerges as an important security primitive in hardware-security applications; it provides an object-specific physical identifier hidden within the intrinsic device variations, which is hard to expose and reproduce by adversaries. Yet, designing a compact PUF robust to noise, temperature and voltage remains a challenge. This thesis presents a novel PUF design approach based on a pair of ultra-compact analog circuits whose output is proportional to absolute temperature. The proposed approach is demonstrated through two works: (1) an ultra-compact and robust PUF based on voltage-compensated proportional-to-absolute-temperature voltage generators that occupies 8.3× less area than the previous work with the similar robustness and twice the robustness of the previously most compact PUF design and (2) a technique to transform a 6T-SRAM array into a robust analog PUF with minimal overhead. In this work, similar circuit topology is used to transform a preexisting on-chip SRAM into a PUF, which further reduces the area in (1) with no robustness penalty. In this thesis, we also explore techniques for power management circuit design. Energy harvesting is an essential functionality in an IoT sensor node, where battery replacement is cost-prohibitive or impractical. Yet, existing energy-harvesting power management units (EH PMU) suffer from efficiency loss in the two-step voltage conversion: harvester-to-battery and battery-to-load. We propose an EH PMU architecture with hybrid energy storage, where a capacitor is introduced in addition to the battery to serve as an intermediate energy buffer to minimize the battery involvement in the system energy flow. Test-case measurements show as much as a 2.2× improvement in the end-to-end energy efficiency. In contrast, with the drastically reduced power consumption of IoT nodes that operates in the sub-threshold regime, adaptive dynamic voltage scaling (DVS) for supply-voltage margin removal, fully on-chip integration and high power conversion efficiency (PCE) are required in PMU designs. We present a PMU–load co-design based on a fully integrated switched-capacitor DC-DC converter (SC-DC) and hybrid error/replica-based regulation for a fully digital PMU control. The PMU is integrated with a neural spike processor (NSP) that achieves a record-low power consumption of 0.61 µW for 96 channels. A tunable replica circuit is added to assist the error regulation and prevent loss of regulation. With automatic energy-robustness co-optimization, the PMU can set the SC-DC’s optimal conversion ratio and switching frequency. The PMU achieves a PCE of 77.7% (72.2%) at VIN = 0.6 V (1 V) and at the NSP’s margin-free operating point.

模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。 / 在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。 / 1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。 / 2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。 / 為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。 / Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design. / In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues: / (1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality. / (2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution. / In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Cui, Guxin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Physical Design --- p.2 / Chapter 1.3 --- Analog Placement --- p.4 / Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4 / Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5 / Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6 / Chapter 1.4.1 --- Process Variation --- p.6 / Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7 / Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9 / Chapter 1.6 --- Problem Formulation of Placement --- p.9 / Chapter 1.7 --- Motivations --- p.10 / Chapter 1.8 --- Contributions --- p.11 / Chapter 1.9 --- Thesis Organization --- p.12 / Chapter 2 --- Literature Review on Analog Placement --- p.13 / Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14 / Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14 / Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16 / Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17 / Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19 / Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20 / Chapter 2.1.6 --- Center-based Corner Block List --- p.22 / Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25 / Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25 / Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27 / Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28 / Chapter 2.3 --- Summary --- p.31 / Chapter 3 --- Common-Centroid Analog Placement --- p.32 / Chapter 3.1 --- Problem Formulation --- p.33 / Chapter 3.2 --- Overview of Our Work --- p.35 / Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37 / Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38 / Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44 / Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47 / Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50 / Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51 / Chapter 3.4.2 --- Layout Expansion --- p.56 / Chapter 3.5 --- Simulated Annealing --- p.59 / Chapter 3.5.1 --- Types of Moves --- p.59 / Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59 / Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61 / Chapter 3.6 --- Summary --- p.62 / Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64 / Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64 / Chapter 4.2 --- Monte Carlo Simulations --- p.70 / Chapter 4.2.1 --- Devices Modeling --- p.70 / Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71 / Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73 / Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74 / Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76 / Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79 / Chapter 5 --- Conclusion --- p.86 / Bibliography --- p.87

Tsang, Ka Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract / Acknowledgement / Content / Chapter 1. --- Introduction / Chapter 1.1 --- Motivation for Current-Mode Circuit --- p.1-1 / Chapter 1.2 --- Basic Current-Mode Building Block --- p.1-3 / Chapter 1.3 --- Adjoint Principle --- p.1-5 / Chapter 1.4 --- Characteristics of Current Amplifier --- p.1-8 / Chapter 1.5 --- Application of Current-Mode Circuit --- p.1-10 / Chapter 2. --- Conventional Design / Chapter 2.1 --- System Overview --- p.2-1 / Chapter 2.2 --- First Architecture and Circuit (Fully Current Mode) --- p.2-6 / Chapter 2.3 --- Second Architecture and Circuit (Voltage Mode) --- p.2-10 / Chapter 2.4 --- Performance Indicator --- p.2-15 / Chapter 3. --- Proposed Design / Chapter 3.1 --- Design Motivation --- p.3-1 / Chapter 3.2 --- Saturation Voltage Gain Stage (SVGS) --- p.3-7 / Chapter 3.3 --- Design 1: Current Amplifier with Boosted Saturation Voltage (Fully Current Mode) --- p.3-13 / Chapter 3.4 --- Design 2: Current Amplifier with Boosted Saturation Voltage (Voltage Mode) --- p.3-22 / Chapter 4. --- IC Measurement / Chapter 5. --- Conclusion / Chapter 5.1 --- Design 1: Current Amplifier with Boosted Saturation Voltage (Fully Current Mode) over Conventional Design --- p.5-1 / Chapter 5.2 --- Design 2: Current Amplifier with Boosted Saturation Voltage (Voltage Mode) over Conventional Design --- p.5-2 / Chapter 6. --- Future Idea / Chapter 7. --- Reference / Chapter 8. --- Appendix

This thesis presents a new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs. We represent the netlist as the binary tree with decision variables associated with each node of the tree. The functionality of the tree nodes is chosen based on the target FPGA architecture. The proposed tree restructuring algorithms preserve local connectivity and allow direct mapping of the trees to the cellular array, thus eliminating the traditional routing phase. Also, predictability of the signal delays is a very important advantage of the developed approach. The developed bus-assignment algorithm efficiently utilizes the medium distance routing resources (buses). The method is general and can be used for any Fine Grain CA-type FPGA. To demonstrate our techniques, ATMEL 6000 series FPGA was used as a target architecture. The area and delay comparison between our methods and commercial tools is presented using a set of MCNC benchmarks. Final layouts of the implemented designs are included. Results show that the proposed techniques outperform the available commercial tools for ATMEL 6000 FPGAs, both in area and delay optimization.