This thesis considers the problem of trajectory generation for robot manipulators along fixed Cartesian paths which contain, or pass near, kinematic singularities. Following a path near singularities can cause very large velocities and accelerations in the robot's joints. Results are presented in this thesis to help understand and cope with this problem. Attention is focused on Cartesian paths which are piecewise analytic. First, it is shown that the joint solutions for such paths can always be expressed, in the neighborhood of a singularity, by means of a fractional power series. This implies a way to smoothly reparameterize the joint solution in the vicinity of a singularity. Second, the Optimal Admissible Timing (OAT) algorithm is presented, which utilizes this reparameterization to generate a minimum-time trajectory along a prescribed path, subject to fixed bounds on the velocities and accelerations of the robot's joints. Finally, an approximate implementation, called the Discrete Admissible OAT (DAO) algorithm, is presented, which works by specifying path velocities at a discrete set of knot points within the path interval. Experimental results are shown for the planar 2R robot and the PUMA robot.

Blind source separation (BSS) attempts to recover a set of statistically independent sources from a set of mixtures knowing only the structure of the mixing network, and the hypothesized probability distribution function of the sources. The case where the sources are immobile persons speaking in a reverberant room is of particular interest, because it represents a first step toward unlocking the so-called "cocktail party problem". Due to the reverberations, BSS in the time domain is usually expensive in terms of computations, but the number of computations can be significantly decreased if separation is carried out in subbands. / An implementation of a subband-based BSS system using DFT filter banks is described, and an adaptive algorithm tailored for subband separation is developed. Aliasing present in the filter bank (due to the non-ideal frequency response of the filters) is reduced by using an oversampled scheme. Experiments, conducted with two-input two-output BSS systems, using both subband and fullband adaptation, indicate that separation and distortion rates are similar for both systems. However, the proposed 32-subband system is approximately 10 times computationally faster than the fullband system.

This thesis focuses on new strategies of designing Optical Code-Division Multiple Access (OCDMA) networks. Specifically, two new spreading code families of 2-dimensional (2D) wavelength-time system are considered: Depth-First Search Codes (DFSC) and Balanced Codes for Differential Detection (BCDD). DFSC utilizes a depth-first search algorithm to generate unipodal codes with maximum unit auto- and cross-correlation properties that are suitable for direct detection. These codes have similar interference-limited bit error rate (BER) performance as most 2D wavelength-time codes, but the algorithm can generate more codes, enabling the full potential of Forward Error Correction (FEC). BCDD defines a new set of high weight antipodal codes with relaxed correlation constraints that is suitable for differential detection. These codes can support approximately twice as many users as the other previously published OCDMA systems. Using a system with 32 wavelengths and 16 time chips operating at OC-12 transmission rates (622Mbps), BCDD can support an aggregate throughput of approximately 136Gbps when proper FEC is applied. / Furthermore, studies on the information theoretical capacity of chip synchronous OCDMA channel with Single User Detection (SUD) is conducted to obtain the ultimate throughput that can be achieved. Calculations are done under three assumptions: (i) interference-limited channel, (ii) interference-limited channel with Gaussian noise; or (iii) Gaussian approximated interference channel. In additions, system specific DFSC and BCDD capacity is obtained. These results are used as the basis for comparison among DFSC, BCDD and other previously proposed OCDMA systems. It is found that the maximum throughput of an OCDMA system is limited to about 0.7 bits per OCDMA chip. With the application of turbo code, BCDD can support an aggregate throughput of about 0.42 bits per OCDMA chip.

This thesis investigates the use of averaging techniques in the development of clock distribution networks and an on-chip clock skew measurement circuit. Our flexible clock distribution network can be used in both single clock and multiple clock integrated circuit applications. The design moves away from clock trees, using a pair of reference clocks traveling in opposite directions to perform clock synchronization on a daisy-chained (serial) clock distribution line. By synchronizing each local clock edge to a position directly in between the forward and reverse reference clock edges, we demonstrate that sub-10 ps variance in clock arrival times can be achieved between local clocks. The design provides a scalable and simple-to-layout solution with multi-point skew compensation useful for large designs. The system provides the benefits of a closed-loop clock de-skewing solution by compensating for process, temperature and power supply variations, with the power savings of an open-loop solution at run-time. Our technique allows routing switches to be included in the clock path, permitting the post-silicon re-sizing and re-shaping of clock domains. Localized clock switches or a complete chip-wide switch mesh can be used to re-route clock signals – a capability that is impossible without our daisy-chained clock network. We investigate a clock network that emphasizes flexibility and reconfigurability without sacrificing tolerance to clock skew. We show that this approach is realizable with transistor-level schematic and extracted circuit structures in TSMC's 180 nm standard process. We also develop a modeling infrastructure from which we can create a variety of clock netwo / Cette thèse étudie une technique de moyennes pour créer un système de distribution d'horloge et un circuit pour mesurer le désalignement de phase d'horloge sur circuit intégré. Notre circuit de distribution d'horloge est polyvalent et peut être employé pour les systèmes avec une horloge simple ou des horloges multiples. La conception s'éloigne des circuits de distribution par arbres, utilisant une paire de signaux de référence voyageant en directions opposées pour corriger le déphasage de chaque horloge répartie linéairement sur la puce. En synchronisant chaque front ascendant d'horloge locale directement entre ceux des signaux de référence, on démontre que le déphasage peut-être réduit en dessous de 10 picosecondes. La conception permet une distribution d'horloges qui est simple à appliquer et extensible. Cette démarche corrige les variations de processus, d'alimentation et de température, fournissant la correction du désalignement de phase systématique de chaque tranche de la distribution d'horloge. Notre technique permet l'introduction des commutateurs de cheminement pour commuter les trajets d'horloge et changer la grandeur et forme des domaines d'horloge après la fabrication d'un circuit intégré. Des commutateurs localisés ou un réseau de commutateur en maille qui couvre le circuit au complet peuvent être utilisés – deux possibilités qui sont impossibles sans notre réseau connecté en série. Notre recherche souligne la flexibilité et la reconfiguration dynamique d'un réseau d'horloge sans sacrifier l'alignement de phase des signaux d'horloges locaux. Nous prouvons que cette approche est réalisable avec des conceptions niv

Reducing the transmission bandwidth and achieving higher speech quality are primary concerns in developing new speech coding algorithms. The goal of this thesis is to improve the perceptual speech quality of algorithms that employ linear predictive coding (LPC). Most LPC-based speech coders extract parameters representing an all-pole filter. This LPC analysis is performed on each block or frame of speech. To smooth out the evolution of the LPC tracks, each block is divided into subframes for which the LPC parameters are interpolated. This improves the perceptual quality without additional transmission bit rate. A method of modifying the interpolation endpoints to improve the spectral match over all the subframes is introduced. The spectral distortion and weighted Euclidean LSF (Line Spectral Frequencies) distance are used as objective measures of the performance of this warping method. The algorithm has been integrated in a floating point C-version of the Adaptive Multi Rate (AMR) speech coder and these results are presented.

I present a distributed vision system for testing and development of computer vision algorithms. The system's form follows a new approach to the construction of vision systems. Utilizing streaming video interconnects and distributed computer resources, the system provides researchers with sufficient processing power to run complex algorithms under real-time constraints. The system runs algorithms in a pipelined mariner, with data passed between functional units using streaming video protocols. DirectShow forms the basis for the system's processing block objects. Researchers can configure the system using functional units from a library of source, rendering, and transform processing blocks available on the system. To aid in configuring the system to the specifications of a given task, I have developed a system management tool that allows the user to configure the system via interaction with a web-based Java applet. This presents the user with a simple, object-oriented framework that is robust and easy to manage.

The process of suppressing acoustic noise in audio signals, and speech signals in particular, can be improved by exploiting the masking properties of the human hearing system. These masking properties, where strong sounds make weaker sounds inaudible, are calculated using auditory models. This thesis examines both traditional noise suppression algorithms and ones that incorporate an auditory model to achieve better performance. The different auditory models used by these algorithms are examined. A novel approach, based on a method to remove a specific type of noise from audio signals, is presented using a standardized auditory model. The proposed method is evaluated with respect to other noise suppression methods in the problem of speech enhancement. It is shown that this method performs well in suppressing noise in telephone-bandwidth speech, even at low Signal-to-Noise Ratios.

Accurate Linear Prediction Coefficient (LPC) estimation is a central requirement in low bit-rate voice coding. Under harsh acoustic conditions, LPC estimation can become unreliable. This results in poor quality of encoded speech and introduces annoying artifacts. / The purpose of this thesis is to develop and test a two-branch speech enhancement pre-processing system. This system consists of two denoising blocks. One block will enhance the degraded speech for accurate LPC estimation. The second block will increase the perceptual quality of the speech to be coded. The goals of this research are two-fold---to design the second block, and to compare the performance of other denoising schemes in each of the two branches. Test results show that the two-branch system can provide better perceptual quality of coded speech over conventional one-branch (i.e., one denoising block) speech enhancement techniques under many noisy environments.

Optoelectronic very-large scale integrated (OE-VLSI) technology provides for the integration of photonic devices, such as the laser-diode and the photodiode, with silicon VLSI electronics. This technology is capable of providing high bandwidth and high-density optical input/output (I/O) to silicon VLSI chips, with an aggregate data bit rate of over a Terabit per second. The development of the vertical-cavity surface-emitting laser (VCSEL) and the high-speed p-i-n photodiode has made this technology possible. Optical transmitter and receiver circuits are responsible for the interfacing between the photonic devices and the silicon VLSI electronics. This thesis presents designs of optical transmitter and receiver circuits implemented in a 0.18 mum CMOS technology. These circuits are designed to achieve minimum power consumption and circuit area, and maximum high-speed performance. Different circuit topologies are studied and implemented. Three different topologies of laser drivers for transmitter and two different preamplifiers for receivers are studied and presented in this thesis.

Recent advances in microelectronics industry allow us to create a System-On-Chip. The embedded memory is one of the vital parts of any system-on-chip. Today it is not enough just to design and fabricate the embedded memory. In order to put the System-On-Chip in mass production, the designer has to be concerned about yield and reliability of the embedded memory. This thesis provides background on fault tolerance improvement theory, and gives several new solutions on how to improve reliability and enhance yield of the embedded memory in efficient ways. / A complete fast embedded SRAM and Control Block for Programmable Clock Manager have been designed, implemented, integrated into a System-On-Chip and tested. The thesis incorporates two novel circuits that significantly improve embedded memory yield and reliability. / This thesis describes new embedded memory architecture for enhanced yield, performance and power consumption. The architecture is able to tolerate major defects including memory kill defects. The mathematical model of the new architecture is presented as well and shows the advantages of new architecture. The new induced Error-Correcting Code (ECC) for Multilevel Dynamic Random Access Memory (MLDRAM) is introduced. The ECC is able to correct 2-bit error and detect 4-bit error. The new ECC also improves reliability and power consumption of the embedded MLDRAM.