RFIC's are traditionally implemented in III--V compounded semiconductors or in bipolar technologies, due to their superior RF performances (e.g. low noise) when compared to CMOS technologies. The challenges are not only to design RF transceivers in standard CMOS processes, but also to establish design methodologies and optimization techniques for their building blocks. / This thesis is concerned with one of the key building blocks, namely the Low Noise Amplifier (LNA). Several low-voltage LNA's were successfully implemented in a standard 0.18 mum CMOS technology, operating in the 5--9 GHz frequency band, targeted for future wireless applications. A new and very simple gain control mechanism is suggested for the first time, which does not affect the optimum noise and impedance matching. The 8--9 GHz prototypes are the highest LNA frequencies reported to-date in CMOS. All prototypes exhibit gain tuning ranges of over 10 dB, and can operate from a supply voltage as low as 0.7 V. / A design strategy for optimizing RF passive components (e.g. inductors, capacitors, and varactors) beyond 5 GHz is presented. / An attempt is made to explore the possibility of using Micro-Electro Mechanical Systems (MEMS) in the RF arena. (Abstract shortened by UMI.)

Due to the continual development of the CMOS IC technology, there is a corresponding strong demand for faster and more accurate methods to compute the delay, which is a critical parameter in CAD tools for timing analysis. Several delay models have been developed for the basic CMOS inverter circuit. These models have also been used in some approaches to the analysis of delay in general CMOS gates. This involves the reduction of the gate to an equivalent inverter. Most gates consist of series and/or parallel combinations of MOSFET transistors. The greatest challenge in the reduction process is presented by the series-connected MOSFET structure (SCMS). In this thesis we examine existing techniques for reducing a SCMS and its input signals to an equivalent transistor with its equivalent input signal. In the process we propose some significant simplifications and improvements to these techniques. / We examine, in particular, the SCMS reduction techniques presented in [5] and [6], both of which use a two-step process consisting of (i) mapping the input signals to a single equivalent one and, (ii) mapping the SCMS transistors to a single MOSFET. The authors of [6] claim that their model is superior to the simpler one used in [5]. Our analysis, based on a 0.35 micron technology, shows that the same accuracy claimed in [6] can be achieved by replacing their Step (ii) by a much simpler one based on the more empirical implementation used on [5]. We also show that the weighting coefficients used by [6] in Step (i) to compute the equivalent input signal, are functions of the input signal transition time, unlike the claim made in [6] that they are constant. We also conclude that, in the final analysis, the accuracy of our modified model as well as the one in [6] is limited by the empirical formula used to determine the equivalent input transition time.

This thesis presents the design of a hardware/software co-simulator and a case study in the comparison of synchronous and asynchronous design styles of digital VLSI circuits. Adopting the design pattern approach of software design, our simulator software package, based on PtolemyII, extracts the temporal causality of software in embedded systems to perform fast timing estimation of functionality partitioning of hardware/software in embedded systems. Our package can simulate system features such as task prioritization, message passing, resource sharing and task blocking. We demonstrate the proposed approach by two event-driven software applications. In this thesis we also discuss synchronous and asynchronous design styles of VLSI circuits. We use a CDMA correlator to illustrate the different aspects of these design styles. The comparison is presented in terms of area and power. Meanwhile, we also include a switching activity study for the evaluation of architecture tradeoffs.

This dissertation investigates the design of optical receivers and transmitters for VLSI chips. The receivers discussed here run at a moderate speed (100's Mb/s) and they need to be relatively sensitive. However, unlike a traditional fiber communication receiver, a low power and area consumption are very important design considerations. The challenge in designing these receivers comes from satisfying simultaneously all the above requirements. The design of VLSI optical transmitters based on reflection-mode modulators is also discussed. Three optoelectronic technologies, namely FET-SEED, MQW diodes flip-chipped onto CMOS, and epitaxy-on-electronic designs were used to design arrays of transceivers. / Current-Mode and buffering techniques are introduced into the design of VLSI-optoelectronic receivers. These techniques enable the integration with the receiver of larger and hence more alignable detectors. The design of a misalignment tolerant array of receivers is proposed and discussed. A time-differential receiver is introduced. It provides the good dynamic range of a dual-rail encoded receiver, but with only half the number of beams. In addition transmitters are optimized to drive large alignable modulators (reflection devices). For this purpose, BiCMOS drivers are also considered and discussed. Low-power adiabatic modulator drivers are proposed. / The designs discussed are multi-purpose and generic to all optical interconnect systems. However, the discussion is performed in the context of the design of a high-capacity free-space optical backplane. An overview of three demonstrator backplanes is given. To guide the design of optical interconnect systems such as a backplane, a model is proposed. It takes into account the important design parameters of the transmitter and receiver. The system model relates the bit error rate (BER) with the optical power of the interconnection (its sensitivity) at any given bit rate for a given design. The model also predicts the power consumption of the interconnect.

This thesis considers the design of receivers for multi-user communication systems based on asynchronous direct-sequence code-division multiple-access (DS-CDMA). Its primary aim is to improve current receiver designs which exhibit shortcomings in systems using long sequence spreading (where the spreading sequence changes with each consecutive bit). The conventional matched filter (MF) and noise-whit MF (NWMF) receivers incur a degradation in performance under power-imbalance (near-far like) conditions. Similar to that of the conventional MF (CMF), the near-far resistance of the NWMF is shown to be zero. Other receivers, including multiuser receivers, suffer from either incompatibility or excessive complexity under long sequence spreading. / Motivated by the need for low-complexity receivers compatible with long sequence spreading, the thesis investigates the design of linear time-invariant (LTI) filters which maximize the signal-to-noise ratio (SNR) for bit symbol detection. It develops the chip-delay locked MF (CLMF) which requires the knowledge of interferer chip delays and signal powers; knowledge of their spreading sequences is unnecessary. Moreover, it takes advantage of the observation that multiple-access interference (MAI) is generally neither white nor stationary, but cyclostationary. Analysis of the CLMF demonstrates that it can deliver non-zero near-far resistance along with performance beyond that of the CMF and NWMF. Furthermore, the computation of the filter response is required only when an interferer signal parameter changes. The complexity of the computation grows linearly with the number of interferers. In addition, insight and directions are presented for the development of adaptive versions of the CLMF which eliminate the need for interferer signal parameters altogether. / Based on the same approach used to develop the CLMF, the thesis presents a general framework from which other one-shot linear detectors can be derived. With increasing knowledge of interferer signal parameters, this approach can synthesize the NWMF, the one-shot linear minimum mean squared error (MMSE) detector and the one-shot decorrelator. Furthermore, the limiting forms of the NWMF and CLMF in the absence of background additive white Gaussian noise (AWGN) are shown to be, respectively, an inverse chip filter followed by a despreading filter (or correlator) and a decorrelator-type CLMF. The thesis also examines how additional knowledge of interferer phase-offsets, the presence of intersymbol interference (ISI) and the presence of both unlocked and chip-delay locked interferers affect filter design.

In this thesis, relay control is applied to a pair of antagonistic Shape Memory Alloy (SMA) actuators for rapid and accurate regulation and tracking of position and force. Similar control is applied for the attenuation of impulse disturbances in the case of vibration isolation. When SMA actuators are used in an antagonistic configuration, relay control has the advantage that the SMA hysteresis is not a concern. This provides a major simplification for the modelling and control of SMA devices. Force and position models for the SMA actuators relevant to control are proposed. Both models are based on a theoretically derived current-stress model for a single SMA fiber. The models are sufficiently true to the original system that control design can be done in simulation and the resultant controllers applied to the actual system without tuning. / Three applications are explored in this work: force control, position control, and impulse disturbance attenuation for vibration isolation. Both the step response and tracking are examined for the constrained force control using a two stage multi-relay controller that switches on the sign of the error. The same two stage controller is used to control position and examine the effects of varying the load on the system. As the applied load increases, the limit cycle magnitude increases, greatly diminishing the accuracy of the response. A position/velocity relay controller is proposed to reduce the limit cycle magnitude to a low level, subject to sensing and sampling rate limitations, even with a difficult undamped inertial load. For vibration isolation, an acceleration/jerk pulse relay controller is presented that rapidly attenuates an impulse disturbance. The presented experimental results set a new standard for accurate and rapid control of SMA devices.

In [12, 13] a theory of hierarchical hybrid control (HHC) was introduced via the formulation of a dynamical consistency (DC) relation between aggregated sets of system states. In the differential control systems case, the state space D of any given continuous base control system S is decomposed by a so-called finite analytic partition pi into a finite set of disjoint open connected blocks. For any such S and pi, a high level finite state control system Mp (called a partition machine of S ) is then obtained from the DC dynamics of the blocks of pi. It is shown that in the class of hybrid in-block controllable (HIBC) partitions the controllability of the base system S is equivalent to the controllability of the partition machine Mp . / Within this context, the converse question naturally arises as to whether any given finite state machine has a representation as the partition machine of some continuous control system S . In Chapter 2, we show that this is indeed the case and we present a constructive solution to this problem for all finite state machines. / The question of finding HIBC partitions leads us to the general study of controllability for nonlinear systems. In Chapter 3, a form of open local accessibility for nonlinear control systems is introduced called the continuous fountain condition. Subject to the condition that (i) the states of a system are continuous fountains, and (ii) one of various recurrence conditions holds; it is established that the system state space is (globally) controllable. It is shown that these controllability results imply the controllability of certain subsets of the state space of Hamiltonian control systems called energy slices. Several algebraic conditions for verification of the fountain property without analysing the actual geometry of accessible sets are established. Finally, these results are shown to have application to HHC theory in that they give conditions for a finite analytic partition to satisfy HIBC hypothesis, / In practice, an application of HHC theory would encounter problems in which the dynamics of the system, the nature of the controllable flows, and the positions of the boundaries of a partition themselves could only be approximately specified, Consequently, it is of interest to establish conditions under which the dynamics of Mp and its associated set of control laws are robust (that is to say insensitive) with respect to sufficiently small perturbations of the partitions defining Mp and small perturbations of the controllable flow. Chapter 4 addresses this issue. Two notions of the deformation of a partition pi are specified as, respectively, maps of the boundaries and the blocks of pi. The robustness properties of the partition machine Mp with respect to deformations of pi, and with respect to deformations of the controllable flow are investigated. / In Chapter 5, HHC theory is generalised to hybrid systems with disturbances. A disturbance rejection hierarchical hybrid control theory is introduced and then applied to a multi-tank example and to a highly simplified air traffic management example.

We base the notion of state aggregation for finite state machines (FSM) on the dynamical consistency (DC) relation ([17]) between the blocks of states in any given state space partition pi. In this framework, we present the new notion of ST dynamical consistency (ST-DC) for source-target (ST) FSMs where there is a preferred sense of flow from a set of source states (S) to a set of target states (T). It is proven that if a partition pi is ST in-block controllable (ST-IBC), the partition machine of an ST FSM M based on pi, Mpi (i.e. high level abstraction of M based on pi), is controllable if and only if M itself is controllable. We also prove that all ST-IBC partition machines of M form a lattice and any chain from the top to the bottom of this lattice provides a hierarchical feedback control structure. / This methodology is next extended to optimal control problems for discrete event systems (DES) modelled by finite state machines. A partition machines based scheme called hierarchically accelerated dynamic programming (HADP) is introduced which significantly speeds up the standard dynamic programming procedure (up to several orders of magnitude) at the cost of a certain degree of sub-optimality. We present necessary and sufficient conditions for the HADP procedure to generate globally optimal solutions and, further, give bounds on the degree of sub-optimality. An example called the Broken Manhattan Grid (BMG) system is used to illustrate the implementation of HADP, and flexible and generalisable code for this example is described. / Many complex systems appear in the form of the product of multiple interacting sub-systems. A formulation of multi-agent systems is presented where the dynamics of the agents are described by default specifications, of a sets of forbidden state-event relational pairs, denoted R . Such systems are called relational multi-agent product systems (MA( R )). The application of the HADP methodology to relational multi-agent product systems is analysed. A multi-machine system consisting of a time counter and agents called a timed multi-agent relational product (TMA( R )) is formulated. / To apply hierarchical control to the routing problem for networks, we consider two conceptual classes of networks: first, link network systems (LN), and, second, buffer network systems (BN). The notions of dynamical costs and network states are introduced. In particular, the notion of throughput-independent ST-IBC (TI-ST-IBC) partitions is used to formulate the incremental HADP ( IHADP) methodology. For the multiple objective optimisation problem of LNs, a notion of (vector) network state is introduced to carry the information describing the available transmission capacity of each link. For buffer network systems, the notion of (matrix) network states is given.

The power industry is undergoing a revolutionary change due to deregulation and associated restructuring. Deregulation is the legislation that governs open access to the transmission grid by competing producing and consuming entities. In this newly-created market structure, bilateral power transactions are emerging as a major trading mechanism. As such, bilateral contracts have become important decision variables in all aspects of power system operation and planning. Consequently, a critical question is how to evaluate the success of any given transaction, especially in the presence of other random simultaneous trades. A successful transaction is understood to be one under which a power system is secure and the proposed trade will be approved as is. This is a necessary condition for the transaction to be economically viable. / The originality of this thesis lies in the integration of random bilateral trading with the physical transmission network. A methodology is developed to estimate the probability of success of any given transaction in the presence of simultaneous random trades with the security requirements of the power system as a given. This measure of success is termed POST (Probability of Secure Transaction). Different forms of POST are defined from the perspectives of the system, the trading partners, or the partners and amount transacted. These and other similar measures form a group of transaction-based security indices. / A Monte Carlo simulation approach is developed as a practical means to estimate the transaction-based security indices. Extensive testing and simulations show that this methodology is effective in transaction risk management, and in network adequacy assessment in the context of random trading. Furthermore, the methodology is used to determine the viability of proposed system reinforcements, especially major power system interconnections involving substantial investments in equipment and resources.

We present an effective method for solving different types of noisy pattern matching problems in Euclidean space. The matching is performed in either a least-squares or a mixed-norm sense under the constraint that a transformation matrix $ Theta$ is restricted to belong to the orthogonal group. Matching problems of this type can be recast as function optimization problems which can be solved by representing the orthogonal group to which $ Theta$ belongs as a Lie group and then investigating the gradient vector field associated with the function to be optimized. The projection of the gradient field onto the tangent space of the Lie group at $ Theta$, i.e., the Lie algebra, results in a descent/ascent equation for the function. The descent/ascent equation so obtained is used in a classical steepest-descent/ascent algorithm and a singular value decomposition-based recursive method in order to determine the maximum or minimum point of the function under consideration. Since $ Theta$ belongs to the orthogonal group which includes the group of permutations as a subgroup, the proposed procedure works not only for patterns consisting of ordered feature points, but also for the combinatorial problem involving patterns having unordered feature points. Generalizations of the matching problem are also formulated and include the matching of patterns from Euclidean spaces of different dimensions and the matching of patterns having unequal numbers of feature points from the same Euclidean space. Simulations are performed which demonstrate the effectiveness and the efficiency of the proposed approach in solving some practical matching problems which arise in computer vision and pattern analysis.