AENT91 and AENT-TTL are AHPL to EDIF netlist translator for the AHPL hardware programming language. Although they are able to provide connections to L-EditTM, GateSimTM and OrCAD/VSTTM some embedded limitations inhibit them from providing more useful connections to other advanced commercial CAD tools. This thesis describes a new AHPL Netlist Format Translator (ANFT) which serves as a multi-target translator with some local optimization processes for AHPL. The limitations of AENT91 and AENT-TTL as well as the design considerations of ANFT are discussed in the first of the three parts of this thesis. Implementation details are provided in the second part. In the last part, tests of ANFT output files and comparisons of results from AENT91, AENT-TTL and ANFT translated AHPL benchmarks are presented. The results show that ANFT not only provides better results but also successfully connects AHPL to more commercial CAD tool systems.

An interest in the application of two-dimensional modulation codes to the coding of information in magnetic recording has lead to an investigation of symbol synchronization for these channels. Binary data storage in magnetic recording systems is accomplished by mapping sequences of 0's and 1's into patterns of magnetic flux changes along a track. With two-dimensional modulation codes, data is encoded in a manner such that clocking information can be derived from any number of those tracks while ensuring against intersymbol interference in each track individually. In this thesis, timing extraction for multiple parallel tracks in the presence of additive white Gaussian noise through a square-law device is studied and the design of the synchronizer circuitry is also presented. Finally, extensive simulations are carried out to determine the performance of the system.

Computed-Aided Design tools have assisted the digital designer at various levels of the design process. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described at the register transfer level. AHPL circuit descriptions can be translated into logic gate networks using the HPCOM hardware compiler. The Electronic Design Interchange Format (EDIF) is a data exchange standard used to exchange data between CAD tools. By providing a translator to convert the logic gate networks from HPCOM into EDIF Netlist format, designs described in AHPL can be ported to other CAD tools. This thesis documents the development and implementation of a EDIF Netlist translator for the HPCOM generated logic network. The translator is designed to use every gate in a package and includes an option that converts logic gates to their NAND equivalents. Netlist outputs from the translator are simulated with the OrCAD Verification and Simulation Tools. These simulations are then compared with simulations from HPSIM to make sure the netlist output from the translator is indeed a gate level representation of the design as described by AHPL.

Electrostatic discharge (ESD) may, depending on the energy of the pulse, cause either catastrophic failures or degradation of MOSFETs. Effects of noncatastrophic positive Human-Body Model (HBM) ESD stress at the gate of power MOSFETs are investigated in this work. Noncatastrophic damage is manifested in the form of positive charge trapping in the gate oxide. In p-channel devices used in this study, the charge injection and trapping occur predominantly in the gate oxide areas lying above the p-body region. In p-channel devices used, the charge is injected mainly from the p-drain region. Based on the polarity of the pulse and the regions observed to contribute to charge injection, a model of ESD-induced charge injection from the silicon into the oxide is proposed. Finally, the effects of noncatastrophic ESD events on the radiation response of n-channel power MOSFETs are reported.

Hardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided.

Low delay speech coding at 16 kbits/sec has received a tremendous amount of attention. One recently proposed scheme that offers excellent performance with buffering delays less than 5 msec is Trellis Coded Quantization (TCQ). The primary objective of this thesis is to evaluate the performance of TCQ in the presence of channel errors. When feedback-free encoding circuits are employed, error propagation is not a serious problem. For encoding sampled speech, segmental signal-to-noise ratios in excess of 20 dB are obtained. Performance comparisons are made using a fixed predictor and four different adaptive predictors for both error-free and noisy channels. Informal listening tests reveal that the reconstructed speech is of "near toll quality" and is almost indistinguishable from the original speech.

Many coordinate systems exist for processing digital color images. The goal of this work was to investigate how the choice of color coordinate system affects the image processing results. Specific issues addressed include (1) quantization error in coordinate transformations, (2) efficient techniques for luminance processing, (3) color space gamut, and (4) color edge detection. The effect of the color coordinate system in each of these areas is explored. Efficient algorithms are presented, along with experimental results using standard color images.

PACnet is a 200-500 Mbps dual-ring fiber optic network designed to implement a Picture Archiving and Communication System (PACS) in a hospital environment. The network consists of three channels: image transfer channel, command and control channel and real-time data channel. An initial network interface unit (NIU) design for PACnet consisted of a functional description of the protocols and NIU major components. Using the International Organization for standards/Open Systems Interconnection (ISO/OSI) reference model as a guide, we extend the definition of the data link layer. This definition covers interface service specifications for the sublayers: logical link control (LLC) and medium access control (MAC). It describes procedures for data transfer, mechanisms of error detection and fault recovery. A performance evaluation study was made to determine the network performance under various scenarios, using stochastic activity networks. The results demonstrate the feasibility of PACnet as an integrated image, data, and voice network for PACS.

Sea-of-Wire Array Logic has been developed to support a symbolic layout algorithm realization. A delay timing scheme is needed to direct the placement strategy of the layout. Both SPICE simulation and table lookup method are compared to verify the accuracy of delay estimation. Input waveform distortion is taken into account in the timing analysis, and correction factors are applied to increase the accuracy of delay estimation. A table lookup scheme has shown to be very accurate in comparison with SPICE value. A set of benchmark circuits have been applied to evaluate this table lookup scheme. The results obtained demonstrate a greater than 90% accuracy and five orders of magnitude increase in speed over SPICE simulation.

The objective of this thesis investigation is to find by computer optimization methods alternate passive realizations for the double resistance terminated low pass Butterworth filters for the third through the tenth order. A second goal is to explain why they exist and to explore other means to derive them. The iterative optimization search performed uses the GOSPEL computer program. New realizations found by this method are presented. Aspects of error and accuracy are discussed as well as a figure of merit test which confirms the validity of the results. Alternate filter realizations produced by selection of left-half-plane zeros for the power reflection coefficient are discussed and a detailed example using this process is performed.