This thesis investigates different methods that can be used for analyzing network performance and,ultimately, can be used for measuring the convergence time of ring coupled networks. As of today,many networks are often run with extra links, serving as backup links in case any that of the mainlinks would go down. To operate networks with backup links in layer 2 and layer 3, specific re-routing protocols such as RIP and OSPF are used in order to calculate a feasible path through anetwork when a network state changes. Depending on different implementations of the protocolsand the hardware used, the convergence times can vary substantially, which means measuring thenetwork performance is a very important part when developing a network solution. To executenetwork tests, a packet engine suite is used consisting of a network traffic generator that is used forcreating a packet stream, as well as a traffic receiver that fetches the packets sent. Various types ofengines can be used including Linux based, real-time operating systems based and bare-metal basedsolutions. From these different types of engines, a few tools are chosen and investigated on differentproperties including performance and usability. It was found that Tshark (Linux, RT-Linux based),USPI (Raspberry Pi bare metal), FreeRTOS (Raspberry Pi based), Arduino and PKTgen (Linuxkernel based) were the most suitable approaches to be used for testing. The test parameters includetesting the gaps between packets, maximum jitter, average jitter and packets sent per second. Thesetests revealed that an IXIA solution was slightly more accurate when used as a receiving end sinceit produced less jitter, however this difference could only be noticed in a micro second range. Itwas also revealed that it produced slightly less jitter than the other packet generators, also here onlynoticeable in a microsecond range. Thus it can be concluded that IXIA is not much superior any ofthe close to hardware solutions. The executed network tests revealed that the Westermo developedlayer 2 protocol FRNT generated less network convergence time and less packet losses than thecommonly used RSTP protocol. Similar tests against the layer 3 protocols revealed that RIP wasmuch faster than OSPF and it also lost less packets. Finally it is concluded that there is no needto buy an expensive network testing suite to test the convergence time of a network. Instead, anetwork testing suite can be developed with minimal funding.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / During the recent years of small satellite space access missions, the trend has been towards designing low-cost ground control centers to maintain the space/ground cost ratio. The use of personal computers (PC) in combination with high speed transputer modules as embedded parallel processors, provides a relatively affordable, highly versatile, and reliable desktop workstation upon which satellite telemetry systems can be built to meet the ever-growing challenge of the space missions today and of the future. This paper presents the feasibility of cost effective, high performance ground systems and a quantitative analysis and study in terms of performance, speedup, efficiency, and the compatibility of the architecture to commercial off the shelf (COTS) tools, and finally, introduces an operational high performance, low cost ground system to strengthen the insight of the concept.

Η εργασία αυτή ερευνά την σχεδίαση ενός σύγχρονου μικροϋπολογιστικού συστήματος βασισμένο σε επεξεργαστή ARM COrtex-M3. Στα πλαίσια αυτής της σχεδίασης έγινε μελέτη των συσκευών που είναι απαραίτητες για την λειτουργία ενός παλμογράφου, και σχεδιάστηκε λογισμικό προσέγγισης της λειτουργίας των βασικών περιφερειακών του. Επιπλέον, γίνεται μια ανάλυση ενός συστήματος απεικόνισης γραφικών, χωρίς την χρήση του μικροελεγκτή, και ποιοτικός σχεδιασμός του συστήματος αυτού. Τέλος, εξάγονται συμπεράσματα για πολυπλοκότητα του σχεδίου και σχολιάζονται οι συμβιβασμοί που είναι απαραίτητοι για την υλοποίηση ενός συστήματος πραγματικού χρόνου. / This thesis analyzes the design of a modern microprocessing system based on an ARM Cortex-M3 microcontroller. For the implemantation of the design thorough research on the necessary peripherals of an oscilloscope is presented and several applications simulating the behavior of its basic functions via its peripherals. Furthermore, a qualitative design is created on a potential graphical processing system, able to fulfill all of the tasks needed to depict on-screen, without burdening the central processor. Conclusions are drawn on the complexity of the design and the tradeoffs of designing a realtime system.

Η εργασία που παρουσιάζεται αφορά την ανάπτυξη ενός ενσωματωμένου συστήματος σε πολλαπλές επαναπρογραμματιζόμενες συσκευές (FPGAs), η επικοινωνία των οποίων γίνεται με τη χρήση του πρωτόκολλου επικοινωνίας TCP/IP. Αρχικά ορίστηκε σε κάθε επαναπρογραμματιζόμενη συσκευή, ένας ενσωματωμένος επεξεργαστής ΜicroBlaze, που ακολουθεί αρχιτεκτονικά την τεχνολογία RISC. Για την κατασκευή της TCP/IP συνδεσιμότητας, αναπτύθηκε σε κάθε core το απαιτούμενο λογισμικό σε γλώσσα προγραμματισμού C, με τη χρήση του open source πρωτοκόλλου επικοινωνίας Light Weight IP. Το συγκεκριμένο πρωτόκολλο είναι ειδικά κατασκευασμένο για σχεδίαση ενσωματωμένων συστημάτων και οι δυνατότητες του οδήγησαν στην ανάπτυξη λογισμικού, προσαρμοσμένο στις απαιτήσεις της ΤCP επικονωνίας και των διαθέσιμων πόρων του επιλεγμένου ενσωματωμένου επεξεργαστή. Η μεταφορά δεδομένων μεταξύ των FPGAs, πραγματοποιήθηκε με την σύνδεση των boards σε έναν μεταγωγέα επιπέδου ζεύξης(Ethernet switch) και Ethernet καλωδίων επικοινωνίας. Ακολούθως, σε κάθε core υλοποίηθηκε σχεδίαση υλικού, η οποία ενσωματώθηκε στο υπόλοιπο υλικό μέσω του διαύλου επικοινωνίας του MicroBlaze επεξεργαστή, με τη μορφή ενός περιφεριακού IP core. Για την επικοινωνία του επιπρόσθετου υλικού με το ενσωματωμένο λογισμικό, χρησιμοποιήθηκαν μηχανισμοί υλικού όπως ουρές δεδομένων εισόδου και εξόδου. Mε αυτόν τον τρόπο, κατέστη δυνατή η ανάπτυξη ενός μηχανισμού που περιλαμβάνει την αποστολή δεδομένων από το κομμάτι του λογισμικού στο υλικό, τη λήψη των δεδομένων από την custom περιφερειακή λογική, την επεξεργασία τους στο κομμάτι του υλικού, την ανάγνωση τους από το λογισμικό και την μετάδοση τους μέσω TCP/IP σύνδεσης σε ένα άλλο αναπτυξιακό, το οποίο μπορεί με τον ίδιο μηχανισμό να επεξεργαστεί τα ληφθέντα δεδομένα. Συμπερασματικά , με έναν αρκετά συμβατό τρόπο , γίνεται εφικτή η κατανομή οποιασδήποτε λογικής σχεδίασης, σε κομμάτια υλικού, τα οποία έχοντας ενσωματωθεί σε ξεχωριστά αναπτυξιακά boards, έχουν τη δυνατότητα να μεταφέρουν και να επεξεργάζονται δεδομένα μεταξύ τους, με χρήση ενός μηχανισμού λογισμικού, υπεύθυνο για τη διαμόρφωση της TCP επικοινωνίας. / This paper presents the development of an embedded system in multiple fpgas, which communicate with each other using ΤCP/IP communication protocol. Initially, a RISC-based embedded MicroBlaze Processor was set, at each device. In order to construct the TCP/IP connectivity, the required software part was developed at each core in programming language C, using the open source communication protocol Light Weight IP. This specific protocol is developed especially for embedded system design and its capabilities allow the construction of a software application, tailored to the requirements of a ΤCP communication and the available resources of the chosen embedded core. The data transfer between the FPGAs, was made with the use of an Ethernet Switch. Each FPGA was connected to an Ethernet switch port via a two directional Ethernet cable. Subsequently, a hardware design was developed at each core, and the custom logic was connected to the MicroBlaze processor local bus as a custom ΙP core peripheral. The communication between the additional hardware part and the embedded software was established with the use of first-in-first-out hardware components for the inputs and outpus of the ΙP core. This led to a successful developed mechanism which includes the transfer of data from software to hardware, the data processing in hardware design, the software reading of the processed data, and finally the data transmission to another FPGA Βoard via TCP/IP communication. In conclusion, a hardware design distribution in multiple FPGAs can be made in a convetional way. The hardware parts, which are embedded in different boards, are able to process, send and receive data across the network, using the appropriate software which is responsible for the configuration of the TCP/IP communication.

Runtime dynamic reconfiguration of field-programmable gate arrays (FPGAs) and devices incorporating microprocessors and FPGA has been successfully utilized to increase performance and reduce power consumption. While previous methods have been successful, they typically do not consider the runtime behavior of the application that can be significantly affected by variations in data inputs, user interactions, and environmental conditions. In this dissertation, we present a dynamically reconfigurable system and design methodology that optimizes performance and power consumption by determining which coprocessors to implement with an FPGA based upon the current application behavior.For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are essential to evaluate the performance and power consumption impact of the hardware coprocessor selection. We present a base profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems.Importantly though, complex interactions between multiple application tasks, non-deterministic execution behavior, and effects of operating system scheduling introduce significant challenges. To address these, we further present an adaptive online performance and power estimation framework suing kernel speedup coefficient adaptation that monitors and adapts the changing application and system behavior for multitasked applications. By exhaustively examining predefined voltage and frequency settings for the microprocessor and hardware kernels, the potential speedup and power reduction can be effectively estimated for each configuration and voltage/frequency settings. These estimates can be utilized to determine the optimal system configuration. At the same time, the kernel speedup coefficients for each kernel can be dynamically updated to account for the difference between the estimated and actual performance measured at runtime.Finally, in order to quickly determine kernel selection and voltage and frequency settlings, we present an efficient, online heuristic performance and power estimation framework that significantly decreases execution time at the cost of a small increase in power consumption. This online heuristic estimation framework achieves significant power reduction compared to software only implementation without performance degradation.

Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dés les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final. Dans cette thèse, nous proposons une méthodologie efficace pour l'estimation de la consommation de puissance des plateformes MPSoC. Cette méthodologie repose sur une combinaison d'une analyse fonctionnelle de la puissance (FLPA) pour l'obtention des modèles de consommation et d'une technique de simulation au niveau transactionnel (TLM) pour calculer la puissance de l'ensemble du système. Fondamentalement, FLPA est proposée pour modéliser le comportement des processeurs en terme de consommation afin d'obtenir des modèles paramétrés de haut niveau. Dans ce travail, FLPA est étendue pour mettre en place des modèles de puissance génériques pour les différentes parties du système (mémoire, logique reconfigurable, etc.). En outre, un environnement de simulation a été développé au niveau transactionnel afin d'évaluer avec précision les activités utilisées dans les modèles de consommation. La combinaison de ces deux parties conduit à une estimation de la puissance hybride qui donne un meilleur compromis entre la précision et la vitesse. La méthodologie proposée a plusieurs avantages: elle estime la consommation du système embarqué dans tous ses éléments et conduit à des estimations précises sans matériel coûteux et complexe. La méthodologie proposée est évolutive pour explorer des architectures complexes embarquées. Notre outil d'estimation de puissance au niveau du système PETS (Power Estimation Tool at System-level) est développé sur la base de la méthodologie proposée. L'efficacité de notre outil PETS en termes de précision et rapidité est validée par des architectures embarquées monoprocesseur et multiprocesseur conçues autour des plateformes OMAP (3530 et 5912) et FPGA Pro Xilinx Virtex II.

The interaction of embedded systems with their environments and their resource limitations make it important to take into account properties such as timing, security, and resource consumption in designing such systems. These so-called Extra-Functional Properties (EFPs) capture and describe the quality and characteristics of a system, and they need to be taken into account from early phases of development and throughout the system's lifecycle. An important challenge in this context is to ensure that the EFPs that are defined at early design phases are actually preserved throughout detailed design phases as well as during the execution of the system on its platform. In this thesis, we provide solutions to help with the preservation of EFPs; targeting both system design phases and system execution on the platform. Starting from requirements, which form the constraints of EFPs, we propose an approach for modeling Non-Functional Requirements (NFRs) and evaluating different design alternatives with respect to the satisfaction of the NFRs. Considering the relationship and trade-off among EFPs, an approach for balancing timing versus security properties is introduced. Our approach enables balancing in two ways: in a static way resulting in a fixed set of components in the design model that are analyzed and thus verified to be balanced with respect to the timing and security properties, and also in a dynamic way during the execution of the system through runtime adaptation. Considering the role of the platform in preservation of EFPs and mitigating possible violations of them, an approach is suggested to enrich the platform with necessary mechanisms to enable monitoring and enforcement of timing properties. In the thesis, we also identify and demonstrate the issues related to accuracy in monitoring EFPs, how accuracy can affect the decisions that are made based on the collected information, and propose a technique to tackle this problem. As another contribution, we also show how runtime monitoring information collected about EFPs can be used to fine-tune design models until a desired set of EFPs are achieved. We have also developed a testing framework which enables automatic generation of test cases in order verify the actual behavior of a system against its desired behavior. On a high level, the contributions of the thesis are thus twofold: proposing methods and techniques to 1) improve maintenance of EFPs within their correct range of values during system design, 2) identify and mitigate possible violations of EFPs at runtime. / CHESS / MBAT / ITS-EASY

This thesis describes novel machine learning techniques specifically designed for use in real-time embedded systems. The techniques directly address three major requirements of such learning systems. Firstly, learning must be capable of being achieved incrementally, since many applications do not have a representative training set available at the outset. Secondly, to guarantee real-time performance, the techniques must be able to operate within a deterministic and limited time bound. Thirdly, the memory requirement must be limited and known a priori to ensure the limited memory available to hold data in embedded systems will not be exceeded. The work described here has three principal contributions. The frequency table is a data structure specifically designed to reduce the memory requirements of incremental learning in embedded systems. The frequency table facilitates a compact representation of received data that is sufficient for decision tree generation. The frequency table decision tree (FTDT) learning method provides classification performance similar to existing decision tree approaches, but extends these to incremental learning while substantially reducing memory usage for practical problems. The incremental decision path (IDP) method is able to efficiently induce, from the frequency table of observations, the path through a decision tree that is necessary for the classification of a single instance. The classification performance of IDP is equivalent to that of existing decision tree algorithms, but since IDP allows the maximum number of partial decision tree nodes to be determined prior to the generation of the path, both the memory requirement and the execution time are deterministic. In this work, the viability of the techniques is demonstrated through application to realtime mobile robot navigation.

Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

Sammanfattning Bakgrund - Dagens processorer börjar närma sig gränsen för hur höga klockfrekvenser de kan köras i. Detta har lett till att processorer har fått fler kärnor för att kunna exekvera flera processer parallellt med flertrådade applikationer. Det finns dock ofta en stor mängd oanvänd beräkningskraft under långa perioder då datorn är igång som ligger i grafikprocessorn, GPU. Då en GPU kan köra tusentals många fler trådar på samma gång än en CPU har ramverk för att göra mer generella beräkningar på GPU utvecklats, dessa kallas för GPGPU-ramverk. Då varje kärna på en GPU inte är lika stark som på en CPU ligger vinsten i att använda algoritmer som går bra att parallellisera. En sådan algoritm är krypteringsalgoritmen AES som är en av de säkraste och vanligaste krypteringsalgoritmerna som används idag. Syfte – Med hjälp av GPU-accelerering kan man kryptera med AES snabbare än med en traditionell CPU-lösning. För att göra GPU-accelereringen så effektiv som möjligt undersöker detta examensarbete vilken AES-metod samt vilket GPGPU-ramverk man bör välja. Metod – För att undersöka vilken/vilka AES-metoder samt vilka GPGPU-ramverk som var lämpliga att använda för denna undersökning gjordes två litteraturstudier. Utifrån data som litteraturstudierna gav genomfördes experiment för att jämföra de valda GPGPU-ramverken med den valda AES-metoden som ansågs vara mest lämpliga. Resultat – Från litteraturstudierna kom det fram att OpenCL och CUDA blir de rekommenderade GPGPU-ramverken och att CTR blir den rekommenderade AES-metoden för AES-kryptering med GPGPU-programmering. Utifrån experimenten som genomförts kunde det konstateras att CUDA är ett effektivare GPGPU-ramverk än OpenCL för AES-CTR på det testade grafikkortet, GTX 560. Implikationer – CUDA är snabbare vid större filer för att OpenCL begränsas mer av dataöverföringshastigheten än CUDA på ett GTX 560. Begränsningar – Experimenten genomfördes endast på ett grafikkort från Nvidia. Eftersom Nvidia inte har något intresse i att optimera för andra GPGPU-ramverk så kunde inte testresultaten från OpenCL verifieras med externa verktyg. Detta p.g.a. att Nvidias verktyg inte längre stödjer debugging eller profiling för OpenCL. Nyckelord – Processorer, GPGPU, AES, CTR, OpenCL, CUDA, GPGPU-ramverk / Abstract Background - Processors today are approaching the limit for how high clockfrequences they can run. This has led to that instead of trying to make them run faster they are instead made with multiple cores so they can utilize parallelization by running several threads in parallel. However aside from the CPU there is still the graphics card which has a large amount of unused computing power for long durations of time while the computer is active. While a GPU might not have as quick processors it instead has several thousands of them at the same time than a CPU which have led to the development of GPGPU-frameworks to use that potential parallelization. The profit in this lies in using algorithms and code functions that got high potential parallelization, one of which is the AES encryption algorithm. AES is one of the most widely used encryption algorithms today and also considered to be one of the most secure. Purpose – By using GPGPU-acceleration the encryption speed of AES is higher than by using a traditional CPU approach. To make the GPU-acceleration as effective as possible this study looks into which AES-method and which GPGPU-framework that should be chosen during development. Method – This study makes two literature studies to determine which AES-methods and which GPGPU-frameworks that are viable for GPU-acceleration of AES. Afterwards this study conducts experiments to determine which of these GPGPU-frameworks are the most effective. Findings – The conclusion drawn from the literature study is that the CTR-method among the AES-methods is preferable due to its parallelization potential and high security measures. Among the current GPGPU-frameworks only two frameworks satisfies the criteria determined from the literature study and those are CUDA and OpenCL. From the experiment the conclusion is thereafter drawn that of the two GPGPU-frameworks CUDA is more effective due to the bandwidth limits that OpenCL have compared to CUDA. This conclusion is valid on at least the tested graphics card, GTX 560. Implications – CUDA is faster at larger file sizes than OpenCL due to limited data transfer speed in OpenCL on a GTX 560. Limitations – The experiments were only conducted on one graphics card from Nvidia due to hardware constraints in that CUDA can only be run on Nvidia hardware. Due to this hardware constraint and Nvidia’s lack of support in their tools for debugging and profiling of OpenCL the results from the testing of OpenCL couldn’t be verified using external tools. Keywords – Processor, GPGPU, AES, CTR, OpenCL, CUDA, GPGPU-framework