Zugl.: Freiburg (Breisgau), Univ., Diss., 2008.

There are two main options for running a program intended for one oper- ating system on a different one. We can modify the program to use the API of the new OS. Alternatively, we can provide a compatibility layer in the new OS, transparent to the program, without changing the application. HelenOS ecosystem already allows the first. This thesis focuses on supporting the lat- ter. This thesis describes the kernel binary interface and analyses existing solutions on Linux, Windows, and specialised systems. Then we describe our prototype that transparently traps syscalls and emulates them. The emula- tion is implemented fully in userspace (except for a small kernel trampoline), and its code is executed in the context of the original application. The result allows running some of the unmodified Linux programs (focusing on GCC toolchain) on the x86_64 instance of the HelenOS system. 1

In recent years, the Internet of Things (IoT) has been proliferating in various fields, such as health care, smart city, and connected autonomous vehicles. Accompanying the popularity of IoT are security attacks that exploit the vulnerabilities of many IoT devices. To build IoT anomaly detection systems, we need to collect and label a large amount data from diverse IoT scenarios, which is a time-consuming and prohibitive task if without the support of an IoT testbed. This thesis fills this urgent need by developing a scalable, flexible, safe, and secure IoT testbed. To make the testbed scalable, we need to reduce the hardware cost and make its architecture easily extendable. For this, we build a hybrid testbed consisting of real IoT devices, such as motion sensors and smart cameras, and emulated devices with Raspberry Pi. The emulated devices can replace real IoT devices with the same operational behaviour as real IoT devices but at a much lower price. Flexibility means the testbed can easily simulate different application scenarios. To make the testbed flexible, we build a dedicated data management module to facilitate the complex tasks in generating diverse traffic patterns, reproducing security attacks, collecting, visualizing, and analyzing network traffic. Testbed safety means the testbed will not cause any adverse impact to the Internet, and testbed security means protecting it from outside attacks. For safety, we carefully analyze the source code and the behaviour of launched attacks and configure a traffic filter to strictly contain the attack traffic within the testbed. For security, we scan and analyze the security of all IoT devices within the testbed to ensure no exposed vulnerability in the used devices. / Graduate

ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / RF Communication (COMMS) systems where receivers and transmitters are in motion must be proven rigorously over an array of natural RF link perturbations such as Carrier Doppler shift, Signal Doppler shift, delay, path loss and noise. These perturbations play significant roles in COMMS systems involving satellites, aircraft, UAVs, missiles, targets and ground stations. In these applications, COMMS system devices must also be tested against increasingly sophisticated intentional and unintentional interference, which must result in negligible impact on quality of service. Field testing and use of traditional test and measurement equipment will need to be substantially augmented with physics-compliant channel emulation equipment that broadens the scope, depth and coverage of such tests, while decreasing R&D and test costs and driving in quality. This paper describes dynamic link emulation driven by advanced antenna and motion modeling, detailed propagation models and link budget methods for realistic, nominal and worst-case hardware-in-the-loop test and verification.

Pietro Perugino's oeuvre is characterized by the reappearance of figures and motifs replicated through the reuse of cartoons. Perugino's deliberate self-plagiarism, despite being rooted in quattrocento compositional methods, exhibits an exploitation of the reproductive nature of the cartoon. While this practice allowed him to develop an efficient design process, the results of this imitation endowed Perugino's work with a formulaic quality, as was first noted by Giorgio Vasari in his Lives of the Most Eminent Painters, Sculptors and Architects (1568). Significantly, in the sixteenth century, theorists revised the concept of imitation to incorporate not only the notion of replication, but emulation as well. An examination of Perugino's reproductive practices alongside this revised view of imitation elucidates the nature of Vasari's criticism, ultimately revealing why the critic placed him among artists of the quattrocento, rather than that of the cinquecento.

Stuttgart, Univ., Diss.,

Stuttgart, Univ, Fachstudie, 2006.

The lack of analytical models that can accurately describe large-scale networked systems makes empirical experimentation indispensable for understanding complex behaviors. Research on network testbeds for testing network protocols and distributed services, including physical, emulated, and federated testbeds, has made steady progress. Although the success of these testbeds is undeniable, they fail to provide: 1) scalability, for handling large-scale networks with hundreds or thousands of hosts and routers organized in different scenarios, 2) flexibility, for testing new protocols or applications in diverse settings, and 3) inter-operability, for combining simulated and real network entities in experiments. This dissertation tackles these issues in three different dimensions. First, we present SVEET, a system that enables inter-operability between real and simulated hosts. In order to increase the scalability of networks under study, SVEET enables time-dilated synchronization between real hosts and the discrete-event simulator. Realistic TCP congestion control algorithms are implemented in the simulator to allow seamless interactions between real and simulated hosts. SVEET is validated via extensive experiments and its capabilities are assessed through case studies involving real applications. Second, we present PrimoGENI, a system that allows a distributed discrete-event simulator, running in real-time, to interact with real network entities in a federated environment. PrimoGENI greatly enhances the flexibility of network experiments, through which a great variety of network conditions can be reproduced to examine what-if questions. Furthermore, PrimoGENI performs resource management functions, on behalf of the user, for instantiating network experiments on shared infrastructures. Finally, to further increase the scalability of network testbeds to handle large-scale high-capacity networks, we present a novel symbiotic simulation approach. We present SymbioSim, a testbed for large-scale network experimentation where a high-performance simulation system closely cooperates with an emulation system in a mutually beneficial way. On the one hand, the simulation system benefits from incorporating the traffic metadata from real applications in the emulation system to reproduce the realistic traffic conditions. On the other hand, the emulation system benefits from receiving the continuous updates from the simulation system to calibrate the traffic between real applications. Specific techniques that support the symbiotic approach include: 1) a model downscaling scheme that can significantly reduce the complexity of the large-scale simulation model, resulting in an efficient emulation system for modulating the high-capacity network traffic between real applications; 2) a queuing network model for the downscaled emulation system to accurately represent the network effects of the simulated traffic; and 3) techniques for reducing the synchronization overhead between the simulation and emulation systems.

Der vorliegende Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Optimierung von Hardware Emulatoren durch die Anwendung von Methoden der partiellen Laufzeitrekonfiguration. An aktuelle Schaltkreis- und Systementwürfe werden zunehmend divergente Anforderungen gestellt. Einer sehr kurzen Entwicklungszeit für eine schnelle Markteinführung steht, um teure und aufwändige Re-Desings zu verhindern, eine möglichst umfangreiche Testabdeckung des Entwurfs gegenüber. Um die Zeit für die Tests zu reduzieren, kommen überwiegend FPGA-basierte HW-Emulatoren zum Einsatz. Durch den Einfluss der steigenden Komplexität aktueller Entwürfe auf die Emulator-Plattform reduziert sich jedoch signifikant die Performance der Emulatoren. Die in Emulatoren eingesetzten FPGAs sind aber zunehmend partiell zur Laufzeit rekonfigurierbar. Der in der vorliegenden Arbeit umgesetzte Ansatz behandelt die Anwendung von Methoden der Laufzeitrekonfiguration auf dem Gebiet der Hardware-Emulation. Dafür ist zunächst eine Partitionierung des zu testenden Entwurfs in möglichst funktional unabhängige Systemteile notwendig. Für eine optimierte und ressourceneffiziente Platzierung der einzelnen HW-Module während der Emulation, ist ein ebenfalls auf dem FPGA platziertes Kommunikationsnetzwerk implementiert. Der vorgestellte Ansatz wird an verschiedenen Beispielen anschaulich illustriert. So kann der Leser die Mächtigkeit der entwickelten Methodik nachvollziehen und wird motiviert, das Verfahren auch auf weitere Anwendungsfälle zu übertragen. / Current circuit and system designs consist a lot of gate numbers and divergent requirements. In contrast to a short development and time to market schedule, the needs for perfect test coverage and quality are rising. One approach to cover this problem is the FPGA based functional test of electronic circuits. State of the art FPGA platforms doesn't consist enough gates to support fully custom designs. The thesis catches this problem and gives some approaches to use partial dynamic reconfiguration to solve the size problem. A fully automated design flow demonstrates partial partitioning of designs, modifications to use dynamic reconfiguration and its schedule. At the end of the work, some examples demonstrates the power of the approach.

Der vorliegende Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Optimierung von Hardware Emulatoren durch die Anwendung von Methoden der partiellen Laufzeitrekonfiguration. An aktuelle Schaltkreis- und Systementwürfe werden zunehmend divergente Anforderungen gestellt. Einer sehr kurzen Entwicklungszeit für eine schnelle Markteinführung steht, um teure und aufwändige Re-Desings zu verhindern, eine möglichst umfangreiche Testabdeckung des Entwurfs gegenüber. Um die Zeit für die Tests zu reduzieren, kommen überwiegend FPGA-basierte HW-Emulatoren zum Einsatz. Durch den Einfluss der steigenden Komplexität aktueller Entwürfe auf die Emulator-Plattform reduziert sich jedoch signifikant die Performance der Emulatoren. Die in Emulatoren eingesetzten FPGAs sind aber zunehmend partiell zur Laufzeit rekonfigurierbar. Der in der vorliegenden Arbeit umgesetzte Ansatz behandelt die Anwendung von Methoden der Laufzeitrekonfiguration auf dem Gebiet der Hardware-Emulation. Dafür ist zunächst eine Partitionierung des zu testenden Entwurfs in möglichst funktional unabhängige Systemteile notwendig. Für eine optimierte und ressourceneffiziente Platzierung der einzelnen HW-Module während der Emulation, ist ein ebenfalls auf dem FPGA platziertes Kommunikationsnetzwerk implementiert. Der vorgestellte Ansatz wird an verschiedenen Beispielen anschaulich illustriert. So kann der Leser die Mächtigkeit der entwickelten Methodik nachvollziehen und wird motiviert, das Verfahren auch auf weitere Anwendungsfälle zu übertragen. / Current circuit and system designs consist a lot of gate numbers and divergent requirements. In contrast to a short development and time to market schedule, the needs for perfect test coverage and quality are rising. One approach to cover this problem is the FPGA based functional test of electronic circuits. State of the art FPGA platforms doesn't consist enough gates to support fully custom designs. The thesis catches this problem and gives some approaches to use partial dynamic reconfiguration to solve the size problem. A fully automated design flow demonstrates partial partitioning of designs, modifications to use dynamic reconfiguration and its schedule. At the end of the work, some examples demonstrates the power of the approach.