Unlike infrastructure-based networks, mobile ad hoc networks consist of nodes independent of any infrastructure. Cooperation among these nodes is essential for the sustenance of multi hop communication. However, battery and bandwidth constraints may lead nodes in an ad hoc network to adopt energy- and bandwidth-conserving strategies. As routing and packet forwarding are end results of cooperation, network performance is affected when nodes in the network behave selfishly to conserve their resources. Our work involves characterizing selfish behavior by nodes in ad hoc networks and assessing the effectiveness of adopting tit for tat based strategies, which are meant to discourage selfish behavior in the network. We show that in an ad hoc network where other nodes act selfishly to conserve their resources, a node can benefit by adopting a generous tit for tat strategy. We also show that a node can gain benefit by avoiding selfish nodes in an ad hoc network, adopting a strategy that we call generous tit for tat with selfish avoidance (GTFT-SA) To analyze the effectiveness of cooperation strategies in selfish ad hoc networks we create an emulation environment based on virtualization. Such an emulation environment is more flexible to changes and is simpler to replicate than real life testbeds, while providing higher fidelity than simulations. / Master of Science

Für das Virtual Reality-Labor des Instituts für Wirtschaftsinformatik der Universität Leipzig sollen Alternativen zu den bestehenden Steuerungsmöglichkeiten gefunden, an die Anlage angeschlossen und evaluiert werden. Es werden Vorgehensweisen dargelegt, die den Anschluss neuer Geräte ermöglichen sowie deren Anwendung am Beispiel der Nintendo Wii-Remote gezeigt.

De nombreux aspects de notre vie courante reposent sur l'échange de données grâce à des systèmes de communication électroniques. Des algorithmes de chiffrement puissants garantissent alors la sécurité, la confidentialité et l'authentification de ces échanges. Néanmoins, ces algorithmes sont implémentés dans des équipements qui peuvent être la cible d'attaques. Plusieurs attaques visant les circuits intégrés sont rapportées dans la littérature. Parmi celles-ci, les attaques laser ont été rapportées comme étant très efficace. Le principe consiste alors à illuminer le circuit au moyen d'un faisceau laser afin d'induire un comportement erroné et par analyse différentielle (DFA) afin de déduire des informations secrètes.L'objectif principal de cette thèse est de fournir des outils de CAO efficaces permettant de sécuriser les circuits en évaluant les contre-mesures proposées contre les attaques laser et cela très tôt dans le flot de conception.Cette thèse est effectuée dans le cadre d'une collaboration étroite entre deux laboratoires de Grenoble INP : le LCIS et le TIMA. Ce travail est également réalisé dans le cadre du projet ANR LIESSE impliquant plusieurs autres partenaires, dont notamment STMicroelectronics.Un modèle de faute au niveau RTL a été développé afin d’émuler des attaques laser. Ce modèle de faute a été utilisé pour évaluer différentes architectures cryptographiques sécurisées grâce à des campagnes d'injection de faute émulées sur FPGA.Ces campagnes d'injection ont été réalisées en collaboration avec le laboratoire TIMA et elles ont permis de comparer les résultats obtenus avec d'autres modèles de faute. De plus, l'approche a été validée en utilisant une description au niveau layout de plusieurs circuits. Cette validation a permis de quantifier l'efficacité du modèle de faute pour prévoir des fautes localisées. De plus, en collaboration avec le CMP (Centre de Microélectronique de Provence) des injections de faute laser expérimentales ont été réalisées sur des circuits intégrés récents de STMICROELECTRONICS et les résultats ont été utilisés pour valider le modèle de faute RTL.Finalement, ce modèle de faute RTL mène au développement d'une contremesure RTL contre les attaques laser. Cette contre-mesure a été mise en œuvre et évaluée par des campagnes de simulation de fautes avec le modèle de faute RTL et d'autres modèles de faute classiques. / Many aspects of our current life rely on the exchange of data through electronic media. Powerful encryption algorithms guarantee the security, privacy and authentication of these exchanges. Nevertheless, those algorithms are implemented in electronic devices that may be the target of attacks despite their proven robustness. Several means of attacking integrated circuits are reported in the literature (for instance analysis of the correlation between the processed data and power consumption). Among them, laser illumination of the device has been reported to be one important and effective mean to perform attacks. The principle is to illuminate the circuit by mean of a laser and then to induce an erroneous behavior.For instance, in so-called Differential Fault Analysis (DFA), an attacker can deduce the secret key used in the crypto-algorithms by comparing the faulty result and the correct one. Other types of attacks exist, also based on fault injection but not requiring a differential analysis; the safe error attacks or clocks attacks are such examples.The main goal of the PhD thesis was to provide efficient CAD tools to secure circuit designers in order to evaluate counter-measures against such laser attacks early in the design process. This thesis has been driven by two Grenoble INP laboratories: LCIS and TIMA. The work has been carried out in the frame of the collaborative ANR project LIESSE involving several other partners, including STMicroelectronics.A RT level model of laser effects has been developed, capable of emulating laser attacks. The fault model was used in order to evaluate several different secure cryptographic implementations through FPGA emulated fault injection campaigns. The injection campaigns were performed in collaboration with TIMA laboratory and they allowed to compare the results with other state of the art fault models. Furthermore, the approach was validated versus the layout of several circuits. The layout based validation allowed to quantify the effectiveness of the fault model to predict localized faults. Additionally, in collaboration with CMP (Centre Microélectronique de Provence) experimental laser fault injections has been performed on a state of the art STMicroelectronics IC and the results have been used for further validation of the fault model. Finally the validated fault model led to the development of an RTL (Register Transfer Level) countermeasure against laser attacks. The countermeasure was implemented and evaluated by fault injection campaigns according to the developed fault model, other state of the art fault models and versus layout information.

På uppdrag av Projektengagemang AB i Skövde har detta projekt genomförts för att studera möjligheten att kvalitetssäkra automationsprojekt bättre med hjälp av emulering. I projektets sammanhang innebär det att representera hela eller delar av automationssystemet virtuellt. För att lyckas med projektet har forskning inom områden som projektledning och virtuella miljöer studerats för att undersöka vad som i dagsläget är möjligt att genomföra. Med hjälp av litteraturen utformades ett intervjuprotokoll för genomförande av en intervjustudie. Beställande och levererande företag av automationsutrustning har bidragit för att ge en realistisk bild av hur automationsprojekt genomförs, kvalitetssäkras samt vad som idag är problematiskt. Sammanställningen och analysen av intervjustudien tyder på att vikt skall läggas vid planering och nedbrytning av projekt, för att ha en tydlig plan från början. Samt att virtuella miljöer kan användas för att testa programkod tidigare i projekt, alltså i mindre kritiska lägen. Efter en granskning av Projektengagemangs förutsättningar i förhållande till intervjustudien framkom att det finns brister och förbättringspotential gällande programstruktur och kvalitetssäkring. Förslaget för att öka kvalitetssäkringen med hjälp av emulering innefattar skapandet av ett arbetskoncept där en emuleringsmodell tillsammans med en kravspecifikation används för framtagning av ett grundprogram. Samt att företagets konstruktionsgranskning utökas till att inkludera kontroll av både programmering och eventuell emuleringsmodell. I förslaget till Projektengagemang lämnas 2 olika konfigurationer som skulle kunna användas för att inkludera skapandet och användning av emuleringsmodeller i projekt. Vilket skulle öka kvalitetssäkringen markant. I dagsläget påverkas inte ledtiden markant med införandet av emulering, dock finns möjligheten på längre sikt. Ytterligare kravställningar behöver tas i beaktning innan val av mjukvaror sker, eftersom förutsättningarna för varje projekt påverkar byggnationen av en emuleringsmodell.

This work deals with verification possibilities of integrated circuits, especially with hardware emulation. The first part of the text briefly describes designing process of an integrated circuit, which includes emulation using emulation platforms. The main part of this work deals with the innovation of the emulation platform, which is used by SCG Czech Design Center s. r. o. Possible ways to improve the current emulation platform are explored and further taken into account when designing a universal emulation platform. Last part of this work deals with functional verification of the proposed universal emulation platform. Functionality will be verified by emulation of the basic control functions of the NCP1246 circuit.

As cyber criminals can find many different ways of gaining unauthorized access to systems without being detected, it is of high importance for organizations to monitor what is happening inside their systems. Adversary emulation is a way to mimic behavior of advanced adversaries within cyber security, which can be used to test detection capabilities of malicious behavior within a system of an organization. The emulated behavior can be based on what have been observed in real cyber attacks - open source knowledge bases such as MITRE ATT&CK collect this kind of intelligence. Many organizations have in recent years developed tools to simplify emulating the behavior of known adversaries. These tools are referred to as adversary emulation tools in this thesis. The purpose of this thesis was to evaluate how noisy different adversary emulation tools are. This was done through measurements on the amount of event logs generated by Sysmon when performing emulations against a Windows system. The goal was to find out which tool was the least noisy. The different adversary emulation tools included in this thesis were Invoke-AtomicRedTeam, CALDERA, ATTPwn and Red Team Automation. To make sure the correlation between the adversary emulation tools and the generated event logs could be identified, a controlled experiment was selected as the method for the study. Five experiments were designed including one emulation scenario each, executed by the different adversary emulation tools included in each experiment. After each emulation, event logs were collected, filtered, and measured for use in the comparison. Three experiments were conducted which compared Invoke-AtomicRedTeam, CALDERA, and a manual emulation. The results of the first three experiments indicated that Invoke-AtomicRedTeam team was the noisiest, followed by CALDERA, and the manual emulation was the least noisy. On average, the manual emulation generated 83,9% fewer logs than Invoke-AtomicRedTeam and 78,4% fewer logs than CALDERA in experiments 1-3. A fourth experiment compared Red Team Automation and Invoke-AtomicRedTeam, where Red Team Automation was the least noisy tool. The final fifth experiment compared ATTPwn and CALDERA, and the results indicated that these were similarly noisy but in different ways. It was also concluded that a main difference between the adversary emulation tools was that the number of techniques available differed between the tools which could limit the ability to emulate the behavior of real adversaries. However, as the emulation tools were implemented in different ways, this thesis could be one starting point for future development of silent adversary emulation tools or to assist in selecting an existing adversary emulation tool.

Volvo is continually updating and replacing their equipment and want to investigate the possibility to shorten the time it takes to implement changes and shorten the time in commissioning projects. The use of an emulation model of a production cell can shorten the commissioning time since the equipment and sequence of the cell can be thoroughly tested before implementation. Volvo also wants to investigate the possibility to validate equipment using emulation. The main objectives are to find an emulation software that suits Volvo’s needs and build an emulation model of an actual production cell at Volvo called G750. A literature review was performed in which the authors gained knowledge about virtual commissioning, simulation and emulation and the usage of these. A market survey was conducted in order to find emulation software that could handle Volvo’s complex production equipment consisting of ABB robots and Siemens PLC. A method for building emulation models of existing production equipment was found during the literature review. The software used to build the emulation model was Simumatik3D. Other software used to make the model as realistic as possible includes RobotStudio, WinCC and PLCSIM. The emulation model handles approximately 350 inputs and outputs. When the emulation model was finished experiments were conducted in order to answer research questions and to reach the main objectives. The experiments validate that the emulation model is representative of the real production cell regarding programming, fail scenarios and movement.

The evolution of the industry, known as industry 4.0, has introduced new technologies such as Virtual Commissioning and Industrial Internet of things. Nowadays, virtual models of automated systems are being created in order to be tested while being built in real life, what includes PLC programs, robots, etc. In order to provide a real behaviour emulation, these virtual models should be as similar to reality as possible. Currently, the components communication in a real system is done through Internet with the use of fieldbuses I/O modules. Right now, these modules are not integrated in the virtual model, as the PLC program returns an error due to the hardware not being found. This implies that the PLC project must be modified, and a workaround must be done in order to connect the I/O cards components of the modules. Furthermore, it means that two PLC projects need to be maintained at the same time, one for the real system and another for the virtual system. In this thesis, a research was done to prove if fieldbuses modules could be emulated, helping to improve Virtual Commissioning. The final goal is to allow a PLC project created for a real system to be run again the corresponding virtual model without any change. To achieve this, a driver able to emulate the communication behaviour of an Ethernet/IP fieldbus module is developed and tested against a real PLC program.

In this thesis, we study the development of linguistic concepts (corresponding to a subset of nouns, verbs and adjectives) on a humanoid robot. To accomplish this goal, we use affordances, a notion first proposed by J.J. Gibson to describe the action possibilities offered to an agent by the environment. Using the affordances formalization framework of Sahin et al., we have implemented a learning system on a humanoid robot and obtained the required data from the sensorimotor experiences of the robot. The system we developed (1) can learn verb, adjective and noun concepts, (2) represent them in terms of strings of prototypes and dependencies based on affordances, (3) can accurately recognize the concept of novel objects and events, and (4) can be used for tasks such as goal emulation and multi step planning.

<p>Binary recompilation and translation play an important role in computer systems today. It is used by systems such as Java and .NET, and system emulators like VMWare and VirtualPC. A dynamic binary translator have several things in common with a regular compiler but as they usually have to translate code in real-time several constraints have to be made, especially when it comes to making code optimisations.</p><p>Designing a dynamic recompiler is a complex process that involves repetitive tasks. Translation tables have to be constructed for the source architecture which contains the data necessary to translate each instruction into binary code that can be executed on the target architecture. This report presents a method that allows a developer to specify how the source and target architectures work using a set of scripting languages. The purpose of these languages is to relocate the repetitive tasks to computer software, so that they do not have to be performed manually by programmers. At the end of the report a simple benchmark is used to evaluate the performance of a basic IA32 emulator running on a PowerPC target that have been implemented using the system described here. The results of the benchmark is compared to the results of running the same benchmark on other, existing, emulators in order to show that the system presented here can compete with the existing methods used today.</p><p>Several ongoing research projects are looking into ways of designing binary translators. Most of these projects focus on ways of optimising code in real-time and how to solve the problems related to binary translation, such as handling self-modifying code.</p>