In this thesis, a novel fully self-aligned bulk-Si device named dual-channel source/drain-tied (DC-SDT) MOSFET with extremely thin (ET) body is proposed. The process utilizes the multiple epitaxial growths of SiGe/Si layers, so the starting material is bulk-Si wafer instead of the SOI wafer. We have investigated the RF/analog performance, and the high temperature induced device stability degradation has also been also investigated. Moreover, we have compared this structure with the other similar transistors such as: body-tied MOSFET (DC-BT MOSFET) and conventional dual-channel MOSFET (DC-SOI MOSFET). Based on the simulation results, for the DC-BT MOSFET, our proposed DC-SDT MOSFET has improved the device performances such as: Ioff decreased 47.6%, switching speed increased 18.1%, S.S. improved 13%, and voltage gain increased 25%. Whereas for the DC-SOI MOSFET, our proposed DC-SDT MOSFET has also improved the device performances such as: Ion increased 11.3%, reduction of lattice temperature 35.7% and 35.5 in the top and bottom channels, voltage gain increased 15%. We not only compared with the above two similar transistors, but also compared to the other mainstream devices, such as: FinFET and Gate-all-around. After the comparisons, we confirm that the proposed DC-SDT MOSFET has better ON-state current and short-channel behaviors. For the scaling, DC-SDT MOSFET can truly become one of the strong candidates.