In this thesis, a novel fully self-aligned bulk-Si device named dual-channel source/drain-tied (DC-SDT) MOSFET with extremely thin (ET) body is proposed. The process utilizes the multiple epitaxial growths of SiGe/Si layers, so the starting material is bulk-Si wafer instead of the SOI wafer. We have investigated the RF/analog performance, and the high temperature induced device stability degradation has also been also investigated. Moreover, we have compared this structure with the other similar transistors such as: body-tied MOSFET (DC-BT MOSFET) and conventional dual-channel MOSFET (DC-SOI MOSFET). Based on the simulation results, for the DC-BT MOSFET, our proposed DC-SDT MOSFET has improved the device performances such as: Ioff decreased 47.6%, switching speed increased 18.1%, S.S. improved 13%, and voltage gain increased 25%. Whereas for the DC-SOI MOSFET, our proposed DC-SDT MOSFET has also improved the device performances such as: Ion increased 11.3%, reduction of lattice temperature 35.7% and 35.5 in the top and bottom channels, voltage gain increased 15%. We not only compared with the above two similar transistors, but also compared to the other mainstream devices, such as: FinFET and Gate-all-around. After the comparisons, we confirm that the proposed DC-SDT MOSFET has better ON-state current and short-channel behaviors. For the scaling, DC-SDT MOSFET can truly become one of the strong candidates.

In this thesis work, novel planar nanodiodes (PNDs) using an amorphous indium-gallium-zinc oxide (IGZO) film as the active layer have been electrically characterised for the first time. Simulation techniques and experimental methods, such as e-beam lithography (EBL) and nanoimprint lithography (NIL), have been explored for these devices. In addition, a novel approach was realized that produced self-aligned contacts for the nanostructured devices. A preliminary parameter space for experimentation of the PNDs was ascertained by simulating the devices using a technology computer aided design (TCAD) simulator. In this study Silvaco’s ATLAS default IGZO material system was adopted. These simulations showed device performance to be heavily dependent on the carrier concentration of the film, owing to the high leakage current during the off-state of device operation. Furthermore, device geometry had a significant influence on the device’s electrical response. Channel width, length and trench width were all examined. Experimental characterisation of PNDs were attained by fabricating devices using EBL. These devices are the first to exhbit diode-like DC electrical response from an IGZO-based PND. Full current rectification was obtained with a rectification ratio of 10^4 for devices with a long, narrow channel with a width of 50nm and a length of 4μm. This particular device geometry had a turn-on voltage, Von, of 2.2V and did not breakdown within the −10V bias range tested. An output drive current of 0.1μA at 10V was obtained by the single PND device. It was also demonstrated that by increasing the channel width, Von could be reduced; however, rectification also diminished. It is reasoned that the exposed IGZO surface was subject to contamination from the ambient which changed the device’s electrical response after 17 days. An ultraviolet NIL (UV-NIL) technique was developed to produce the PNDs. This fabrication method offers a suitable route towards high-volume manufacture of these nanodevices, which is critical for them to be incorporated into a low-cost RF energy harvester. A novel NIL process was established in which the contact pads were self-aligned to within ~ 200nm of the channel by patterning both metal and semiconductor layers with a single imprint. DC electrical characterisation of the imprinted PNDs produced high rectifications ratios at a lower Von. The greater number of devices tested allowed a coarse parameter space for channel width and length to determined. PNDs with a channel aspect ratio (length divided by width) of more than 20 exhibited the greatest DC rectification of 10^4. An alumina capping layer was found to eliminate hysteresis in the electrical response; however, the greater permittivity value had no noticeable effect on device performance. Finally, a large-signal RF analysis is carried out on a device which suggest no deterioration in device perfromance up to at least 1GHz.

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed. / text

Les mémoires flash sont intégrées dans presque tous les aspects de la vie moderne car leurs uns et zéros représentent les données stockées sur les cartes à puce et dans les capteurs qui nous entourent. Dans les mémoires flash à grille flottante ces données sont représentées par la quantité de charge stockée sur une grille en poly-Si, isolée par un oxyde tunnel et un diélectrique entre grilles (IGD). Au fur et à mesure que les chercheurs et les ingénieurs de l'industrie microélectronique poussent continuellement les limites de mise à l'échelle, la capacité des dispositifs à contenir leurs informations risque de devenir compromise. Même la perte d'un électron par jour est trop élevée et entraînerait l'absence de conservation des données pendant dix ans. Étant trop faibles, les courants de fuite sont impossible à mesurer directement. Cette thèse présente une nouvelle méthode, la séparation du stress aux oxydes (OSS), pour mesurer ces courants en suivant les changements de la tension de seuil de la cellule flash. La nouveauté de la technique est que les conditions de polarisation sont sélectionnées afin que le stress se produise entièrement dans l'IGD, permettant la reconstruction d'une courbe IV de l'IGD à des tensions faibles. Cette thèse décrit également les changements de processus nécessaires pour intégrer la première mémoire flash embarquée de 40 nm basée sur un IGD d'alumine, en remplacement du SiO2/ Si3N4/SiO2 standard. L'intérêt pour les matériaux high-k vient de la motivation de créer un IGD qui est électriquement mince pour augmenter le couplage tout en étant physiquement épais pour bloquer le transport de charge. Comme la flash intégrée au noeud de 40 nm se rapproche de la production, l'approche à prendre dans les nœuds futurs doit également être discutée. Cela fournit la motivation pour le chapitre final de la thèse qui traite de la co-intégration des différents IGD avec des dispositifs logiques ayant les gilles « high-k metal » nécessaires à 28 nm et au-delà. / Flash memory circuits are embedded in almost every aspect of modern life as their ones and zeros represent the data that is stored on smart cards and in the sensors around us. In floating gate flash memories this data is represented by the amount of charge stored on a poly-Si gate, isolated by a tunneling oxide and an Inter Gate Dielectric (IGD). As the microelectronics industry’s researchers and engineering continuously push the scaling limits, the ability of the devices to hold their information may become compromised. Even the loss of one electron per day is too much and would result in the failure to retain the data for ten years. At such low current densities, the direct measurement of the leakage current is impossible. This thesis presents a new way, Oxide Stress Separation, to measure these currents by following the changes in the threshold voltage of the flash cell. The novelty of the technique is that the biasing conditions are selected such that the stress occurs entirely in the IGD, allowing for the reconstruction of an IV curve of the IGD at low biases. This thesis also describes the process changes necessary to integrate the world’s first 40 nm embedded flash based on an alumina IGD, in replacement of the standard SiO2/Si3N4/SiO2. The interest in high-k materials comes from the motivation to make an IGD that is electrically thin to increase coupling while being physically thick to block charge transport. As embedded flash at the 40 nm node nears production, the approach to be taken in future nodes must also be discussed. This provides the motivation for the final chapter of the thesis which discusses the co-integration of the different IGDs with logic devices having the high-k metal gates necessary at 28 nm and beyond.

4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development. To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of &gt;92% are realized. Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process. Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated. This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications. / <p>QC 20170810</p>