Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Kernel methods are able to exploit high-dimensional spaces for representational advantage, while only operating implicitly in such spaces, thus incurring none of the computational cost of doing so. They appear to have the potential to advance the state of the art in control and signal processing applications and are increasingly seeing adoption across these domains. Applications of kernel methods to fault detection and isolation (FDI) have been reported, but few in aerospace research, though they offer a promising way to perform or enhance fault detection. It is mostly in process monitoring, in the chemical processing industry for example, that these techniques have found broader application. This research work explores the use of kernel-based solutions in model-based fault diagnosis for aerospace systems. Specifically, it investigates the application of these techniques to the detection and isolation of IMU/INS sensor faults – a canonical open problem in the aerospace field. Kernel PCA, a kernelised non-linear extension of the well-known principal component analysis (PCA) algorithm, is implemented to tackle IMU fault monitoring. An isolation scheme is extrapolated based on the strong duality known to exist between probably the most widely practiced method of FDI in the aerospace domain – the parity space technique – and linear principal component analysis. The algorithm, termed partial kernel PCA, benefits from the isolation properties of the parity space method as well as the non-linear approximation ability of kernel PCA. Further, a number of unscented non-linear filters for FDI are implemented, equipped with data-driven transition models based on Gaussian processes - a non-parametric Bayesian kernel method. A distributed estimation architecture is proposed, which besides fault diagnosis can contemporaneously perform sensor fusion. It also allows for decoupling faulty sensors from the navigation solution.

The demands of future computing, as well as the challenges of nanometer-era VLSI design, will require new design techniques and design styles that are simultaneously high performance, energy-efficient, and robust to noise and process variation. One of the emerging problems concerns the communication mechanisms between the increasing number of blocks, or cores, that can be integrated onto a single chip. The bus-based systems and point-to-point interconnection strategies in use today cannot be easily scaled to accommodate the large numbers of cores projected in the near future. Network-on-chip (NoC) interconnect infrastructures are one of the key technologies that will enable the emergence of many-core processors and systems-on-chip with increased computing power and energy efficiency. This dissertation is focused on testing, yield improvement and fault-tolerance of such NoC infrastructures. A fast, efficient test method is developed for NoCs, that exploits their inherent parallelism to reduce the test time by transporting test data on multiple paths and testing multiple NoC components concurrently. The improvement of test time varies, depending on the NoC architecture and test transport protocol, from 2X to 34X, compared to current NoC test methods. This test mechanism is used subsequently to perform detection of NoC link permanent faults, which are then repaired by an on-chip mechanism that replaces the faulty signal lines with fault-free ones, thereby increasing the yield, while maintaining the same wire delay characteristics. The solution described in this dissertation improves significantly the achievable yield of NoC inter-switch channels â from 4% improvement for an 8-bit wide channel, to a 71% improvement for a 128-bit wide channel. The direct benefit is an improved fault-tolerance and increased yield and long-term reliability of NoC based multicore systems. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

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Class of 2013 Abstract / Specific Aims: The purpose of this study was to investigate areas of ambiguity or error in the content of prescriptions generated using DrFirst’s electronic prescribing software Rcopia adetermines whether these quality issues are attributed to the software, physician, or both. Methods: Electronic prescriptions generated by DrFirst electronic prescribing software, Rcopia, from July 2012 through September 2012 were analyzed regarding the following metrics: number of free text prescriptions, quantity unit mismatches, and SIG issues. These metrics were expressed as a percentage of the total number of prescriptions generated for each month and used for descriptive analysis. Main Results: The total number of prescriptions generated were 12,043,268, of which 363,142 (3%) were free text (uncoded) and 11,680,126 (97%) were non-free text. SIG as directed was identified in 227,732 prescriptions, of which 11,208 (3.1%) were free text and 216,524(1.9%) were non-free text. Double SIG was identified in 174,625 prescriptions, of which 75,336 (20.1%) were free text and 1,746,250 (14.1%) were non-free text. A total of 830 (0.23%) of free text prescriptions contained a Latin abbreviation. Of 621,816 prescriptions containing a quantity unit error, 7,684 (2.1%) were free text prescriptions and 614,132 (5.3%) were non-free text prescriptions. Conclusion: The authors concluded that the software and physician are responsible for error. There were errors associated with selections made by the prescriber in the drop down menus and coded medications in Rcopia. Furthermore, errors were found in free text prescriptions which must be manually entered by the physician or their staff.

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As users continually request additional functionality, software systems will continue to grow in their complexity, as well as in their susceptibility to failures. Particularly for sensitive systems requiring higher levels of reliability, faulty system modules may increase development and maintenance cost. Hence, identifying them early would support the development of reliable systems through improved scheduling and quality control. Research effort to predict software modules likely to contain faults, as a consequence, has been substantial. Although a wide range of fault prediction models have been proposed, we remain far from having reliable tools that can be widely applied to real industrial systems. For projects with known fault histories, numerous research studies show that statistical models can provide reasonable estimates at predicting faulty modules using software metrics. However, as context-specific metrics differ from project to project, the task of predicting across projects is difficult to achieve. Prediction models obtained from one project experience are ineffective in their ability to predict fault-prone modules when applied to other projects. Hence, taking full benefit of the existing work in software development community has been substantially limited. As a step towards solving this problem, in this dissertation we propose a fault prediction approach that exploits existing prediction models, adapting them to improve their ability to predict faulty system modules across different software projects.

京都大学 / 0048 / 新制・課程博士 / 博士(理学) / 甲第22260号 / 理博第4574号 / 新制||理||1657(附属図書館) / 京都大学大学院理学研究科地球惑星科学専攻 / (主査)教授 岩田 知孝, 教授 福田 洋一, 准教授 宮﨑 真一 / 学位規則第4条第1項該当 / Doctor of Science / Kyoto University / DGAM

With the ever growing complexity of computer-controlled systems, the need for discrete- event systems has emerged. Many contributions have been done to improve and dis- cuss discrete-event system properties. In this thesis, we investigate the problem of fault tolerance in timed discrete-event systems. Our goal is to establish a timed fault tolerant supervisory control approach. We start by presenting our settings and providing different fault scenarios. We then provide four fault tolerant definitions to verify that the system will remain controllable in each scenario. Also, we introduce algorithms to verify timed controllability for each scenario. We implement a tool extension for the software research tool, DESpot, to verify timed controllability. Furthermore, we implement a tool extension to verify fault tolerant untimed controllability and nonblocking, and timed fault tolerant controllability for the fault scenarios. Finally, we present a simple example to illustrate our approach. / Thesis / Master of Applied Science (MASc)

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