A "low cost fault detection system" that identifies wheel flats and defective tracks is explored here. This is achieved with the conjunction of sensors, microcontrollers and Radio Frequency (RF) transceivers. The objective of the proposed research is to identify faults plaguing railcars and to be able to clearly distinguish the faults of a railcar from the inherent faults in the track. The focus of the research though, is mainly to identify wheel flats and defective tracks. The thesis has been written with the premise that the results from the simulation software GENSYS are close to the real time data that would have been obtained from an actual railcar. Based on the results of GENSYS, a suitable algorithm is written that helps segregate a fault in a railcar from a defect in a track. The above code is implemented using hardware including microcontrollers, accelerometers, RF transceivers and a real time monitor. An enclosure houses the system completely, so that it is ready for application in a real environment. This also involves selection of suitable hardware so that there is a uniform source of power supply that reduces the cost and assists in building a robust system.

In recent decades, transient faults have become a critical issue in modernelectronic devices. Therefore, many fault-tolerant techniques have been proposedto increase system reliability, such as active redundancy, which can beimplemented in both space and time dimensions. The main challenge of activeredundancy is to introduce the minimal overhead of redundancy and to schedulethe tasks. In many pervious works, perfect fault detectors are assumed to simplifythe problem. However, the induced resource and time overheads of suchfault detectors make them impractical to be implemented. In order to tacklethe problem, an alternative approach was proposed based on imperfect faultdetectors. So far, only software implementation is studied for the proposed imperfectfault detection approach. In this thesis, we take hardware-acceleration intoconsideration. Field-programmable gate array (FPGA) is used to accommodatetasks in hardware. In order to utilize the FPGA resources efficiently, themapping and the selection of fault detectors for each task replica have to be carefullydecided. In this work, we present two optimization approaches consideringtwo FPGA technologies, namely, statically reconfigurable FPGA and dynamicallyreconfigurable FPGA respectively. Both approaches are evaluated andcompared with the proposed software-only approach by extensive experiments.

The demands of future computing, as well as the challenges of nanometer-era VLSI design, will require new design techniques and design styles that are simultaneously high performance, energy-efficient, and robust to noise and process variation. One of the emerging problems concerns the communication mechanisms between the increasing number of blocks, or cores, that can be integrated onto a single chip. The bus-based systems and point-to-point interconnection strategies in use today cannot be easily scaled to accommodate the large numbers of cores projected in the near future. Network-on-chip (NoC) interconnect infrastructures are one of the key technologies that will enable the emergence of many-core processors and systems-on-chip with increased computing power and energy efficiency. This dissertation is focused on testing, yield improvement and fault-tolerance of such NoC infrastructures. A fast, efficient test method is developed for NoCs, that exploits their inherent parallelism to reduce the test time by transporting test data on multiple paths and testing multiple NoC components concurrently. The improvement of test time varies, depending on the NoC architecture and test transport protocol, from 2X to 34X, compared to current NoC test methods. This test mechanism is used subsequently to perform detection of NoC link permanent faults, which are then repaired by an on-chip mechanism that replaces the faulty signal lines with fault-free ones, thereby increasing the yield, while maintaining the same wire delay characteristics. The solution described in this dissertation improves significantly the achievable yield of NoC inter-switch channels – from 4% improvement for an 8-bit wide channel, to a 71% improvement for a 128-bit wide channel. The direct benefit is an improved fault-tolerance and increased yield and long-term reliability of NoC based multicore systems.

Geomorphological and paleoseismic studies provide insight into the fault geometry and kinematics of a series of dextral northeast striking faults, including the Porters Pass, Hawdon, Bullock Hill, and Esk faults, in the South Island of New Zealand. These faults show post-glacial offsets that are significantly larger than predicted from co-seismic displacement - surface rupture length regressions derived from empirical relationships. Geomorphological mapping reveals slip rates as high as 9 mm/year for the Hawdon fault and Bullock Hill fault over an expected fault length of c. 140 km. Surface expressions of some parts of the studied faults are obscured by glacial gravels, indicating that blind faults are present in parts of the Sourthern Alps and may be the source for a component of a reported slip deficit in North Canterbury. Concluding from comparing scaling relationship results for the individual faults I hypothesize that the Porters Pass, Hawdon, Bullock Hill and Esk faults are segments of an incipient fault system that stretches from the western tip of the Porters Pass fault to the Hope fault, east of Hanmer Springs. Considering the location, similar strike and dextral deformation mode, I suggest that this 140 km long dextral strike-slip fault system marks the southernmost extension of the Marlborough Fault System resulting from the ongoing southward propagation of the Pacific-Australian plate boundary in New Zealand's South Island.

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The aim of this thesis is to extend the current techniques available for the analysis of non-coherent fault trees. At present importance analysis of non-coherent systems is extremely limited. The majority of measures of importance that have been developed can only be used to analyse coherent fault trees. If these measures are used to analyse non-coherent fault trees the results obtained are inaccurate and misleading. Extensions for seven of the most commonly used measures of importance have been proposed to enable accurate analysis of non-coherent systems. The Binary Decision Diagram technique has been shown to provide an accurate and efficient means of analysing coherent fault trees. The application of this technique for the qualitative analysis of non-coherent fault trees has demonstrated the gains to be made in terms of efficiency and accuracy. Procedures for quantifying a non-coherent fault tree using this technique have been developed; these techniques enable significantly more efficient and accurate analysis than the conventional techniques for Fault Tree Analysis. Although the Binary Decision Diagram technique provides an efficient and accurate means of analysing coherent and non-coherent fault trees, large trees with many repeated events cannot always be analysed exactly. In such circumstances partial analysis must be performed if any conclusions regarding system safety and reliability are to be drawn. Culling techniques employed in conjuncfion with the Binary Decision Diagram method have been developed for the partial analysis of both coherent and non-coherent fault trees.

This thesis is aimed at enhancing the existing set of techniques for building distributed systems, specifically from the point of view of fault-tolerant com- puting. Reliability is of fundamental importance in the design and operation of dis- tributed systems, as an increasing number of computers are employed in the automation of various essential services. In the past decade, much research effort has been concerned with the object-based methodology for the design and implementation of reliable distributed systems. This thesis describes three contributions to this effort. First, it is shown that object-based programming features can in fact be introduced into pro- cedural languages provided that these languages are endowed with certain facilities. Then, work is discussed which illustrates the relationship between distributed object-based architectures and an apparently different form of distributed architectures based on processes. This work puts the notion of object-based architectures into a new perspective, which shows that the object-based philosophy and the process-based philosophy are the dual of each other. Finally, an important aspect of the design of an object-based distributed architecture is investigated, that of automatic garbage collection. A distri- buted garbage collection scheme is described that handles fault tolerance by an extension of the technique commonly employed to detect unwanted com- putations in distributed architectures. The scheme proposed can also be seen as yet a further illustration of the link between object-based and process-based architectures.

One way of gaining confidence in the adequacy of fault tolerance mechanisms of a system is to test the system by injecting faults and see how the system performs under faulty conditions. This thesis investigates the issues of testing software-implemented fault tolerance mechanisms of distributed systems through fault injection. A fault injection method has been developed. The method requires that the target software system be structured as a collection of objects interacting via messages. This enables easy insertion of fault injection objects into the target system to emulate incorrect behaviour of faulty processors by manipulating messages. This approach allows one to inject specific classes of faults while not requiring any significant changes to the target system. The method differs from the previous work in that it exploits an object oriented approach of software implementation to support the injection of specific classes of faults at the system level. The proposed fault injection method has been applied to test software-implemented reliable node systems: a TMR (triple modular redundant) node and a fail-silent node. The nodes have integrated fault tolerance mechanisms and are expected to exhibit certain behaviour in the presence of a failure. The thesis describes how various such mechanisms (for example, clock synchronisation protocol, and atomic broadcast protocol) were tested. The testing revealed flaws in implementation that had not been discovered before, thereby demonstrating the usefulness of the method. Application of the approach to other distributed systems is also described in the thesis.