Thesis (Ph. D.)--Rutgers University, 2009. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 151-156).

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 129-145). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--Naval Postgraduate School, 2002. / Thesis advisor(s): Todd Weatherford, Ronald Pieper. Includes bibliographical references (p. 39-40). Also available online.

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--Youngstown State University, 2009. / Includes bibliographical references (leaves 44-45). Also available via the World Wide Web in PDF format.

The fabrication processes development for on III-nitride (III-N) heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs) and metal-insulator-semiconductor field-effect transistors (MISFETs) were performed. D.c, microwave and quasi-static I-V and C-V measurements were carried out to characterize the fabricated III-N transistors and diodes. The GaN/InGaN direct-growth HBTs (DG-HBTs) grown on free-standing GaN (FS-GaN) substrates demonstrated a high current gain (hfe) > 110, high current density (JC) > 141 kA/cm2, and high power density (Pdc) > 3 MW/cm2. The first III-N DG-HBT showing fT > 8 GHz and fmax > 1.3 GHz were also demonstrated on sapphire substrates. Recessed-gate AlGaN/AlN/GaN HFETs demonstrated Vth = 0 V with 0.17 V deviation across the sample. Baliga's figure of merit is 240 MW/cm2 was achieved. Current collapse was eliminated and the dynamic on-resistance was reduced by 67% after using a remote-oxygen-plasma treatment. Normally-off recessed-gate AlGaN/AlN/GaN MISFETs with Vth = 0.9 V were also fabricated with the remote-oxygen-plasma treatment. Low leakage current (< 1 pA/mm), high on-off ratio (> 2.2E11) are achieved. These achievements suggest that high-performance III-N transistors are very promising for high-power switching and microwave amplification. Findings concerning remaining process issues and implications for future research are also discussed.

To overcome the issues of mobility degradation and charge trapping in silicon high-κ MOSFET, a stacked Y₂O₃(top)/HfO2(bottom) gate dielectric on silicon substrate has been developed. Compared to the HfO₂ reference, the new dielectric shows similar scalability, but superior channel mobility and device reliability. The mobility improvement can be attributed to reduced remote phonon scattering, which is associated with the smaller ionic polarization of Y₂O₃, and the suppressed coulomb scattering due to less electron trapping in the bulk of high-κ layer, and reduced metal impurities in the substrate. The passivation mechanisms for the silicon IPL passivation technique in GaAs/[alpha]-Si IPL/high-κ MOS system have been investigated. We demonstrate the [alpha]-Si IPL thickness dependence and substrate type dependence of interface state density (Dit) for GaAs MOS capacitors. The interface state density is strongly correlated to the thickness and quality of un-oxidized Si IPL and its interaction with the underlying substrate. The results can be explained by the models related to the quantum well narrowing or the reduced local trap density as the unoxidized Si IPL layer thickness decreases. By using optimal Si IPL thickness (~10 Å), GaAs MOS devices can achieve the same interface quality, as its silicon counterpart. Using Si IPL to unpin the surface Fermi level, the selfaligned depletion-mode and enhancement-mode GaAs n-MOSFETs are demonstrated. In addition, the charge trapping and wear-out characteristics of the GaAs/Si IPL/HfO2/TaN MOS devices are systematically investigated. High performance In0.53Ga0.47As nMOSFETs with Si IPL and HfO2 gate oxide have been demonstrated. We systematically investigate the impacts of 1) Source/Drain activation temperature, 2) post deposition annealing (PDA) temperature, 3) In[subscrip 0.53]Ga[subscript 0.47]As channel doping concentration, 4) channel thickness and 5) Si IPL thickness on the transistor performances. With the [mu]m, V[subscript d]=50 mV), drive current of 158 mA/mm (L[subscript g]=5 [mu]m, V[subscript gs]=V[subscript th]+2 V, V[subscript d]=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. optimal combination of these impacting factors, excellent device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm, Vd=50 mV), drive current of 158 mA/mm (Lg=5 [mu]m, Vgs=Vth+2 V, Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. / text

This dissertation consists of six chapters: In the first chapter, electrical and material properties and charge transport in organic semiconductors and graphene based field-effect transistors (FETs) are introduced. In the second chapter, device architectures of indenofluorene-phenanthrene copolymer based thin-film transistors (TFTs) are discussed. The combination of recessed source/drain and surface treatments on electrical contact and low-voltage-operated TFTs with solution-processed high-k dielectric are investigated. In the third chapter, device physics and charge transport of diketopyrrolopyrrole-naphthalene copolymer based TFTs are discussed. Top-gate TFTs with the polymer dielectric exhibit mobilities of ~1 cm2/V-s and charge transport measurements in steady-state and under non-quasi-static conditions reveal device physics in dual-gate configuration. In the fourth chapter, device characteristics and charge transport in ambipolar diketopyrrolopyrrole-benzothiadiazole copolymer based TFTs are focused. The ambipolar polymer TFTs possess balanced electron and hole mobilities which are both > 0.5 cm2/V-s. The trap density of states is calculated using two analytical methods developed by Lang et al. and Kalb and Batlogg. In the fifth chapter, charge transport of diketopyrrolopyrrole-thiophene copolymer based TFTs employing 4-point-probe configuration is studied. Such polymer TFTs possess the mobilities of up to 3 cm2/V-s. The activation energy as a function of carrier concentration represents multiple trapping and thermally release model or Monroe-type model of charge transport. In the sixth chapter, transformation of electrical characteristics of graphene FETs with an interacting capping layer of fluoropolymers and pi-conjugated organic semiconductors is investigated. The electrical properties of graphene by wafer-scale chemical vapor deposition can be favorably tuned by fluorocarbon capping methods. / text

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