The purpose of this work is to develop a new model for LDD n-MOSFET degradation in drain current under long-term AC use conditions for lifetime projection which includes a self-limiting effect in the hot-electron induced device degradation. Experimental results on LDD n-channel MOSFETs shows that the maximum drain current degradation is a function of the AC average substrate current under the various AC stress conditions but not a function of frequency or waveforms or different measurement configurations. An empirical model is constructed for circuit applications. It is verified that the self-limiting in drain current is due to the thermal re-emission of a trapped-hot-electron in the oxide. Results show that self-heating during AC stress releases trapped electrons, which in turn limits the maximum amount of drain current degradation. Moreover, tunneling to and from traps model is employed to visualize the internal mechanism of thermal recovery of electrons under different bias conditions. Although the LDD device structure can reduce the hot electron effect, various processing technologies can also affect the device reliability. A carbon doped LDD device with the first and the second level metal and passivation layer but without any final anneal shows that a significant reduction in the shifts of the threshold voltage of MOSFETs with time can be achieved. However, the long-term reliability projection of nMOSFETs based on DC stress tests alone is shown to be overly pessimistic. / Graduation date: 1992

The semiconductor gallium arsenide (GaAs) has many potential advantages over the more widely used semiconductor silicon (Si). These include higher low field mobility, semi-insulating substrates, a direct band-gap, and greater radiation hardness. All these advantages offer distinct opportunities for implementation of new circuit functions or extension of the operating conditions of similar circuits in silicon based technology. However, full exploitation of these advantages has not been realized. This study examines the limitations imposed on conventional GaAs metal-semiconductor field effect transistor (MESFET) technology by deviations of the semi-insulating substrate material from ideal behavior. The interaction of the active device with defects in the semi-insulating GaAs substrate is examined and the resulting deviations in MESFET performance from ideal behavior are analyzed. A p-well MESFET technology is successfully implemented which acts to shield the active device from defects in the substrate. Improvements in the operating characteristics include elimination of drain current transients with long time constants, elimination of the frequency dependence of g[subscript ds] at low frequencies, and the elimination of sidegating. These results demonstrate that control of the channel to substrate junction results in a dramatic improvement in the functionality of the GaAs MESFET. The p-well MESFET RF characteristics are examined for different p-well doping levels. Performance comparable with the conventional GaAs MESFET technology is demonstrated. Results indicate that optimization of the p-well MESFET doping levels will result in devices with uniform characteristics from DC to the highest operating frequency. / Graduation date: 1991

A complete Gallium Arsenide Metal Semiconconductor Field Effect Transistor (GaAs MESFET) model including deep-level trap effects has been developed, which is far more accurate than previous equivalent circuit models, for high-speed applications in linear integrated circuit design. A new self-backgating GaAs MESFET model, which can simulate low frequency anomalies, is presented by including deep-level trap effects which cause transconductance reduction and the output conductance and the saturation drain current to increase with the applied signal frequency. This model has been incorporated into PSPICE and includes a time dependent I-V curve model, a capacitance model, a subthreshold current model, an RC network describing the effective substrate-induced capacitance and resistance, and a switching resistance providing device symmetry. An analytical approach is used to derive capacitances which depend on Vgs and Vds and is one which also includes the channel/substrate junction modulation by the self backgating effect. A subthreshold current model is analytically derived by the mobile charge density from the parabolic potential distribution in the cut-off region. Sparameter errors between previous models and measured data in conventional GaAs MESFET's have been reduced by including a transit time delay in the transconductances, gm and gds, by the second order Bessel polynomial approximation. As a convenient extraction method, a new circuit configuration is also proposed for extracting simulated S-parameters which accurately predict measured data. Also, a large-signal GaAs MESFET model for performing nonlinear microwave circuit simulations is described. As a linear IC design vehicle for demonstrating the utility of the model, a 3-stage GaAs operational amplifier has been designed and also has been fabricated with results of a 35 dB open-loop gain at high frequencies and a 4 GHz gain bandwidth product by a conventional half micron MESFET technology. Using this new model, the low frequency anomalies of the GaAs amplifier such as a gain roll-off, a phase notch, and an output current lag are more accurately predicted than with any other previous model. This new self-backgating GaAs MESFET model, which provides accurate voltage dependent capacitances, frequency dependent output conductance, and transit time delay dependent transconductances, can be used to simulate low frequency effects in GaAs linear integrated circuit design. / Graduation date: 1991

This thesis includes elementary introductions to nuclear quadrupole resonance (NQR) detection and fieldeffect transistors (PET). The construction and operation of the FET-NQR detector, as originally designed by Viswanathan, Viswanathan and Sane and published in Rev. Sci. Instr. 39,472 (1968), is discussed extensively. The thesis also contains a step by step discussion of the construction of an alternate PET-N'QP detector. Although the alternate detector never functioned properly, the information gathered would aid anyone desiring to design and construct a new NQR detector.Ball State UniversityMuncie, IN 47306

This thesis provides the study of graphene’s electrostatic interaction with the substrate surrounding it. Mathematical models based on current experimental configurations of graphene field-effect transistors (FET) are developed and analyzed. The conductivity and mobility of charge carriers in graphene are examined in the presence of impurities trapped in the substrate near graphene. The impurities encompass a wide range of possible structures and parameters, including different types of impurities, their distance from graphene, and the spatial correlation between them. Furthermore, we extend our models to analyze the influence of impurities on the fluctuations of the electrostatic potential and the charge carrier density in the plane of graphene. The results of our mathematical models are compared with current experimental results in the literature.

We studied terahertz radiation from InN in our paper. We set up " Terahertz Time-Domain Spectroscopy system" and investigate Terahertz emission from InN. We take our sample(InN) in the rotation stage and we rotate different angle to detect the THz intensity data and wave shape and also the mechanisms of THz wave emitted. We research the influence from different background carrier density, band gap, mobility and structure(Zb-InN, W-InN) of InN to produce Terahertz radiation. Finally, we dicuss the THz amplitude and shape influenced from the internal surface field effect, Photo Dember effect, stacking fault, c-plane and m-plane from InN.

We have grown the high quality AlGaN/GaN heterostructure by plasma-assisted molecular beam epitaxy. We obtained the mobility of two-dimensional electron gas of the AlGaN/GaN is 9300 cm2/Vs and carrier concentration is 7.9¡Ñ1012 cm-2 by conventional van der Pauw Hall measurement at 77K. The samples made of the AlGaN/GaN heterostructure were patterned to Hall bar geometry with a width of 20£gm by conventional photolithography. After the photolithography, the nanowire was fabricated by the process of focus ion beam (FIB), and the widths of nanowire were reduced to 900 nm, 500 nm, 300 nm, 200nm, 100 nm, 80 nm and 50 nm respectively. The SiO2 layer and Al electrode were deposed on the samples to form nanowired MOSFETs. We have studied the leakage current measurement on the AlGaN/GaN nanowired MOSFETs at 300K. On the 100 nm and 200 nm width of nanowires, we did not observe the leakage current for the gate voltage work range from -2.5 to 3.0 V and from -0.5 to 0.5 V respectively.

The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

Thesis (Ph. D.)--Lehigh University, 2000. / Includes vita. Includes bibliographical references (leaves 132-136).

Thesis (Ph. D.)--Rutgers University, 2009. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 151-156).