This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references.

<p>Chemical gas sensors can be used in a variety of applications such as process control, security systems and medical diagnosis. In the research for new functions and new sensing materials a “breadboard” would be useful. A technique that has been investigated for such a purpose is the grid-gate device which is a metal-oxide-semiconductor (MOS) based gas sensor. It is a MOS capacitor consisting of a passive grid-gate with depositions of sensing materials overlapping the grid. The measuring is carried out with a light addressable method called scanning light pulse technique (SLPT) which enables the detection of spatially distributed gas response.</p><p>A development of the grid-gate sensor would be to separate the sensing materials from the chip. In this thesis the aim was to see if this was possible by depositing the sensing material on a slide of micro pillars which was put on top of a biased grid-gate chip.</p><p>The test was made with palladium depositions in an ambient of synthetic air and 2500 ppm hydrogen, and the measuring technique was SLPT as for the preceding device.</p><p>The result of the test was that the new device showed a combined gas response of both charge content shift at flat-band voltage and at inversion voltages. The conclusion is therefore that the sensing material can be separated from the grid-gate chip and that the response will be caused by several mechanisms. The two-dimensional image response utilized for the preceding grid-gate device will instead be a multi-dimensional response consisting of the curve for the charge content shift at every measuring position.</p>

<p>This report is the result of a diploma work made at Linköping University from August 2006 till September 2007 by Erik Lundin, under the guidance of Doctor Mike Andersson and Professor Anita Lloyd Spetz. Its purpose was to find suitable materials for the construction of an oxygen sensor. The hope was not to construct such a sensor, but to investigate materials that may be suitable in creating one. In the preparatory time period of the diploma work, different papers and books were studied in order to get a proper understanding of the sensor mechanism. During this period of time, a design proposal was made and the theory behind it is presented in this thesis. The main objective in this thesis has been to investigate the response of field effect devices to oxygen and other gases that are compounds in exhaust or flue gases. Devices were created by employing the materials which were investigated. Special material combinations were proposed for field effect devices suitable for oxygen detection by Doctor Mike Andersson. One material combination showed promising results for selective detection of the oxygen concentration in exhaust gases.</p> / This diploma work has been confidential

The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier. / Graduation date: 1999

Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA is the inaccurate high-frequency noise model of the MOSFET implemented in circuit simulators such as SPICE. Silicon-based monolithic inductors are another bottleneck in RF CMOS design due to their poor quality factor. In this thesis, a CMOS implementation of a fully-integrated differential LNA is presented. A small-signal noise circuit model that includes the two most important noise sources of the MOSFET at radio frequencies, channel thermal noise and induced gate current noise, is developed for CMOS LNA analysis and simulation. Various CMOS LNA architectures are investigated. The optimization techniques and design guidelines and procedures for an LC tuned CMOS LNA are also described. Analysis and modeling of silicon-based monolithic inductors and transformers are presented and it is shown that in fully-differential applications, a monolithic transformer occupies less die area and achieves a higher quality factor compared to two independent inductors with the same total effective inductance. It is also shown that monolithic transformers improve the common-mode rejection of the differential circuits. / Graduation date: 1999

High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 232-237).

This Ph.D. thesis focuses on the high-frequency electrical capabilities of the carbon-nanotube, field-effect transistor (CNFET). The thesis can be categorized into three stages, leading up to an assessment of the RF capabilities of realistic array-based CNFETs. In the first stage, the high-frequency and time-dependent behavior of ballistic CNFETs is examined by numerically solving the time-dependent Boltzmann transport equation (BTE) self-consistently with the Poisson equation. The RF admittance matrix, which contains the transistor’s y-parameters, is extracted. At frequencies below the transistor’s unity-current-gain frequency fT, the y-parameters are shown to agree with those predicted from a quasi-static equivalent circuit, provided that the partitioning factor for the device charge is properly extracted. It is also shown that a resonance behavior exists in the transistor’s y-parameters. In the second stage, non-quasi-static effects in ballistic CNFETs are examined by analytically developing a transmission-line model from the BTE and Poisson equation. This model includes nonclassical transistor elements, such as the "quantum capacitance" and "kinetic inductance," and it is shown to represent the intrinsic (contact-independent) transistor’s behavior at high frequencies, including a correct prediction of the resonances in the y-parameters. Moreover, it is shown that the kinetic inductance can be represented using lumped elements in the transistor’s small-signal equivalent circuit, and it is demonstrated that the resulting circuit is capable of modeling intrinsic CNFET behavior to frequencies beyond fT. In the last stage, by building upon the first two stages, a comprehensive study is performed to assess the RF performance potential of array-based CNFETs. First, phonon scattering is incorporated into the time-dependent BTE to study the impacts of collisions on different aspects of intrinsic CNFET operation, including the intrinsic fT and the small-signal equivalent circuit. These results are then further extended by adding the effects of extrinsic (contact-dependent) parasitics and then examining the behavior of key RF figures of merit, such as the extrinsic fT, the attainable power gain, and the unity-power-gain frequency. The results are compared to those of state-of-the-art high-frequency transistors and to the next generation of RF CMOS, and they provide an indication of the potential advantages of array-based CNFETs for RF applications. / Micro-Electro-Mechanical Systems (MEMS) and Nanosystems