Abstract This study investigates the waves and current field interaction with a perforated floating breakwater which is fastened by tension lags. As the predecessor done, the porous media governing equation is adopted inside the perforated floating breakwater, but a control volume concept has been applied in the breakwater in order to find the external forces on the system. A new dispersion equation has been introduced with the fact of the uniform current influence on the reflection waves (moving upstream direction) and the transmission waves (moving downstream direction). Since the whole system belongs to a domain problem and also assumes it can be linearlized, a boundary element method (BEM) is developed to solved the problem. To confirm this new BEM is correct and accuracy, a zero current has been set and compared its results with analytical solutions that was published by the predecessor. The comparison between the new BEM and analytical solutions has good agreements. It means the BEM developed by this paper has its own accuracy. Based on the same numerical model, a floating breakwater and waves/current interaction problems are investigated. The results have shown that the uniform current will degrade the reflection coefficients but increase the transmission coefficients. In general, the perforated floating breakwater, which is deeper under the water and longer in width, has smaller transmission coefficients. But practically when designing a perforated floating breakwater, we still suggest to increase the width rather than to deepen the depth. It is because the effects of dissipating wave energy are more obvious when increasing the width.

Jung Jeng Lake located in Mei Nong in south of Taiwan, is the origin of Mei Nong Hakka culture. Owing to stockbreeding hogs, cultivation and domestic wastewater in the upstream of Jiang Tz Liau River that finally flows into Jung Jeng Lake for years, the lake thus suffered extremely serious problem of eutrophication. In addition, the water hyacinth remain seeds in the lake and reproduce resulting in speeding up the lacustrine silt that would greatly shorten the life of Jung Jeng Lake. Using artificial lagoon and artificial floating island were found able to improve the water quality of lake. Therefore, we could sightseeing resource, historic site, and ecological resources of Mei Nong. This research applied the advantages of ecological engineering methods to restore the Jung Jeng Lake, and thus the southern Taiwan unique Hakka tourism can be presented.

Computer models are nowadays routinely used in harbor engineering applications. Models based on the two-dimensional elliptic mild-slope equation can simultaneously simulate refraction, diffraction, reflection, and dissipation in completely arbitrary coastal domains. However, floating structures such as floating breakwaters and docks are often encountered in the modeling domain. This makes the problem locally 3- dimensional. Hence it is problematic to incorporate a floating structure into the 2-d model. Tsay and Liu (1983) proposed a highly simplified but approximate approach to handle this problem practically. The validity of their approach is examined in detail and it is found that the actual solutions deviate considerably from the theoretical solutions, although their approximation provides results with the correct trend. Therefore, correction factors have been developed and may be used to produce more reliable results using the framework of Tsay and Liu (1983). The resulting method is applied to Douglas harbor in Alaska. The result shows that docks in the harbor distort the wave field considerably and create a reflective pattern that can affect navigation safety in some areas. Also plots are developed for the transmission coefficients for waves propagating past rectangular and cylindrical floating objects of infinite extent for a wide range of conditions encountered in practice.

Floating-point multipliers are typically power hungry which is undesirable in many embedded applications. This paper proposes a variable-latency floating-point multiplier architecture, which is suitable for low-power, high-performance, and high-accuracy applications. The architecture splits the significand multiplier into upper and lower parts, and predicts the required significand product and sticky bit from upper part. In the case of correct prediction, the computation of lower part is disabled and the rounding operation is significantly simplified so that floating-point multiplication can be completed early. Finally, detailed design and simulation of the floating-point multiplier is presented, together with its evaluation by comparing power consumption with the fast and conventional floating-point multipliers. Experimental results demonstrate that the proposed double-precision multiplier consumes up to 26.41% and 24.97% less power and energy than the fast floating-point multiplier respectively at the expense of only small area and delay overhead. In addition, the results also show that the performance of proposed floating-point multiplier is very approximate to that of fast floating-point multipliers.

Floating-point arithmetic is attractive for the implementation for a variety of Digital Signal Processing (DSP) applications because it allows the designer and user to concentrate on the algorithms and architecture without worrying about numerical issues. In the past, many DSP applications used fixed point arithmetic due to the high cost (in delay, silicon area, and power consumption) of floating-point arithmetic units. In the realization of modern general purpose processors, fused floating-point multiply add units have become attractive since their delay and silicon area is often less than that of a discrete floating-point multiplier followed by a floating point adder. Further the accuracy is improved by the fused implementation since rounding is performed only once (after the multiplication and addition). This work extends the consideration of fused floating-point arithmetic to operations that are frequently encountered in DSP. The Fast Fourier Transform is a case in point since it uses a complex butterfly operation. For a radix-2 implementation, the butterfly consists of a complex multiply and the complex addition and subtraction of the same pair of data. For a radix-4 implementation, the butterfly consists of three complex multiplications and eight complex additions and subtractions. Both of these butterfly operations can be implemented with two fused primitives, a fused two-term dot-product unit and a fused add-subtract unit. The fused two-term dot-product multiplies two sets of operands and adds the products as a single operation. The two products do not need to be rounded (only the sum is normalized and rounded) which reduces the delay by about 15% while reducing the silicon area by about 33%. For the add-subtract unit, much of the complexity of a discrete implementation comes from the need to compare the operand exponents and align the significands prior to the add and the subtract operations. For the fused implementation, sharing the comparison and alignment greatly reduces the complexity. The delay and the arithmetic results are the same as if the operations are performed in the conventional manner with a floating-point adder and a separate floating-point subtracter. In this case, the fused implementation is about 20% smaller than the discrete equivalent. / text

Floating-point computer arithmetic units are used for modern-day computers for 2D/3D graphic and scientific applications due to their wider dynamic range than a fixed-point number system with the same word-length. However, the floating-point arithmetic unit has larger area, power consumption, and latency than a fixed-point arithmetic unit. It has become a big issue in modern low-power processors due to their limited power and performance margins. Therefore, fused architectures have been developed to improve floating-point operations. This dissertation introduces new improved fused architectures for add-subtract, sum-of-squares, and magnitude operations for graphics, scientific, and signal processing. A low-power dual-path fused floating-point add-subtract unit is introduced and compared with previous fused add-subtract units such as the single path and the high-speed dual-path fused add-subtract unit. The high-speed dual-path fused add-subtract unit has less latency compared with the single-path unit at a cost of large power consumption. To reduce the power consumption, an alternative dual-path architecture is applied to the fused add-subtract unit. The significand addition, subtraction and round units are performed after the far/close path. The power consumption of the proposed design is lower than the high-speed dual-path fused add-subtract unit at a cost in latency; however, the proposed fused unit is faster than the single-path fused unit. High-performance and low-power floating-point fused architectures for a two-term sum-of-squares computation are introduced and compared with discrete units. The fused architectures include pre/post-alignment, partial carry-sum width, and enhanced rounding. The fused floating-point sum-of-squares units with the post-alignment, 26 bit partial carry-sum width, and enhanced rounding system have less power-consumption, area, and latency compared with discrete parallel dot-product and sum-of-squares units. Hardware tradeoffs are presented between the fused designs in terms of power consumption, area, and latency. For example, the enhanced rounding processing reduces latency with a moderate cost of increased power consumption and area. A new type of fused architecture for magnitude computation with less power consumption, area, and latency than conventional discrete floating-point units is proposed. Compared with the discrete parallel magnitude unit realized with conventional floating-point squarers, an adder, and a square-root unit, the fused floating-point magnitude unit has less area, latency, and power consumption. The new design includes new designs for enhanced exponent, compound add/round, and normalization units. In addition, a pipelined structure for the fused magnitude unit is shown. / text

The ePUMA architecture is a novel master-multi-SIMD DSP platform aimed at low-power computing, like for embedded or hand-held devices for example. It is both a configurable and scalable platform, designed for multimedia and communications. Numbers with both integer and fractional parts are often used in computers because many important algorithms make use of them, like signal and image processing for example. A good way of representing these types of numbers is with a floating-point representation. The ePUMA platform currently supports a fixed-point representation, so the goal of this thesis will be to implement twelve basic floating-point arithmetic operations and two conversion operations onto an already existing datapath, conforming as much as possible to the IEEE 754-2008 standard for floating-point representation. The implementation should be done at a low hardware and power consumption cost. The target frequency will be 500MHz. The implementation will be compared with dedicated DesignWare components and the implementation will also be compared with floating-point done in software in ePUMA. This thesis presents a solution that on average increases the VPE datapath hardware cost by 15% and the power consumption increases by 15% on average. Highest clock frequency with the solution is 473MHz. The target clock frequency of 500MHz is thus not achieved but considering the lack of register retiming in the synthesis step, 500MHz can most likely be reached with this design.

Processors used in lower-end scientific applications like graphic cards and video game consoles have IEEE single precision floating-point hardware [23]. Double precision offers higher precision at higher implementation cost and lower performance. The need for high precision computations in these applications is not enough to justify the use double precision hardware and the extra hardware complexity needed [23]. Native-pair arithmetic offers an interesting and feasible solution to this problem. This technique invented by T. J. Dekker uses single-length floating-point numbers to represent higher precision floating-point numbers [3]. Native-pair arithmetic has been proposed by Dr. William R. Dieter and Dr. Henry G. Dietz to achieve better accuracy using standard IEEE single precision floating point hardware [1]. Native-pair arithmetic results in better accuracy however it decreases the performance by 11x and 17x for addition and multiplication respectively [2]. The proposed implementation uses a residual register to store the error residual term [2]. This addition is not only cost efficient but also results in acceptable accuracy with 10 times the performance of 64-bit hardware. This thesis demonstrates the implementation of a 32-bit floating-point unit with residual register and estimates the hardware cost and performance.

This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magnitude improvement over existing solutions restricted to using only one type computational domain. To that end, I have helped build large and complicated reconfigurable systems (and software tools for helping to use these systems) capable of implementing solutions to problems in all three of those domains simultaneously. These systems are used to explore and implement these cross domain solutions to difficult problems. The earlier work was involved with simply applying floating-gate technology to improving the building blocks of digital systems. Through that early work a new logic family built from floating-gate transistors was discovered, a Logical Effort compatible power analysis technique was developed, and low power floating-gate based FPGA was implemented. This work was then merged with existing research in the group involving solving problems using reconfigurable analog, and neuromorphic techniques. Thus converging on the mentioned systems that allow one to solve problems using techniques from all three domains: analog, neuromorphic, and digital.

The study of infinitely long cylinders of constant cross-section floating in an infinite fluid bath in zero-gravity environments has primarily been focused on bodies whose cross-sections are strictly convex and sufficiently smooth. In this thesis, our efforts are concentrated on the consideration of bodies that are only convex and piecewise smooth. These types of bodies are seldom considered in current literature. We have worked with a series expansion of the energy function in order to determine when configurations of a given body will be in equilibrium, stable or otherwise. We have proven that any convex body with a straight side cannot float in a stable equilibrium with the fluid interface intersecting the interior of the straight side in a single point. This fact is then used to prove necessary and sufficient conditions for stable equilibrium of polygons, bodies whose cross-sections are comprised of only straight sides. We illustrate these conditions with several examples. In the latter portion of the thesis, we turn our attention to bodies in three dimensions. While past research has again been focused on strictly convex bodies, we began to consider bodies that do not meet these requirements by examining bodies of revolution. A condition for stability with respect to vertical variations of bodies of revolution is derived. We conclude with several examples of bodies of revolution, some of which interestingly relate back to an analogous two-dimensional shape.