A compact frequency synthesizer based on a phase locked loop (PLL) is designed for the self-calibration in RF circuits. The main advantage of the presented frequency synthesizer is that it can be built in a small silicon area using MOSFET interface trap charge pump (ITCP) current generators. The ITCP current generator makes it possible to use small currents at nano-ampere levels so that small capacitances can be used in the loop filter. A large resistance, which is required to compensate for the reduced capacitances, is implemented using an operational transconductance amplifier (OTA). An ITCP current generator is used as a tail current source for the OTA in order to realize a small transconductance. The presented frequency synthesizer has the output frequency range from 570 MHz to 600 MHz with a 100 KHz frequency step. Total silicon area is about 0.3 mm2 using AMIS 0.5 ??m CMOS technology, and the power consumption is 26.7 mW with 3 V single power supply.

This thesis includes two topics. The first topic is a programmable DLL-based frequency multiplier, which can be a local oscillator in RF applications. The second one is a ROM-less direct digital frequency synthesizer to serve as a good reference clock or to be used in digital modulation and demodulation. A CMOS local oscillator using a programmable DLL-based frequency multiplier is presented. In this work, low-Q on-chip inductors are not needed. The clock of the output frequency is digitally controllable, which is ranged from 7´ to 10´ of an input reference clock. The design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The output frequency range of the physical chips measurement is about 1.0 GHz ~ 1.5 GHz. Maximum power dissipation is 58.2 mW at 1.5 GHz output. A ROM-less direct digital frequency synthesizer (DDFS) employing trigonometric quadruple angle formula is presented. In a system-level simulation, the spurious tones performance is suppressed to be lower than -130 dBc. The resolution is up to 13 bits. The maximum error is also analyzed mathematically to meet the simulation results.

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In this proposal, an advanced local oscillator with high resolution, low phase noise and fast switching characteristics is designed for wireless communication applications. The circuit is based on fractional-N frequency synthesis technique in which the use of delta-sigma modulator can remove the fractional spurs effectively. The mechanism in regard to fractional spurs and phase noise for a fractional-N frequency synthesizer will be studied and simulated by developing proper mathematical models. In the implementation of the local oscillator, the analog circuit includes a 1000-1033 MHz VCO, crystal oscillator and loop filter. The digital circuit includes a phase frequency detector, dual modulus divider and 3rd order delta-sigma modulator. At first a FPGA will be used to prototype the digital circuit. The final digital circuit will be implemented in a CMOS process and require 3V operation with low current consumption. The design specifications include that under 1 KHz resolution the phase noise levels are less than -90 dBc/Hz at frequency offets within a loop bandwidth more than 100 KHz. Spurious components are less than -90 dBc/Hz and switching time is less than 1 ms over a 30 MHz tuning range.

An ISM-band frequency synthesizer is introduced in this thesis. The technique allows digital phase/frequency modulation to be achieved in a closed phase locked loop (PLL) without mixers and D/As. According to the simulation results using ADS, quantization noise will be filtered by the PLL bandwidth. But the data rate is also bounded by the PLL bandwidth. Two key components of this closed-loop architecture, Gaussian filter and delta-sigma modulator have been implemented by FPGA together with the Qualcomm Q3236 synthesizer IC.

This dissertation presents a 2.4 GHz wideband GFSK-modulated frequency synthesizer using two-point delta-sigma modulation (TPDSM). The two bottlenecks in this design have been rigorously investigated. One bottleneck is the nonlinear performance of the phase-locked loop (PLL). The other one is the inherent gain and delay mismatch between the two modulation points. Both nonlinear and mismatch factors dominate the modulation accuracy in the closed PLL. The proposed formulation can successfully predict the dependencies of the modulation accuracy on both factors. The comparison of the averaged frequency deviation and frequency-shift -keying (FSK) error between theory and measurement shows excellent agreement. The modulated frequency synthesizer implemented in this study can achieve a 2.5 Mbps data rate as well as a 15 £gs PLL stable time with only 2.2 % FSK error under good design and operating conditions.

Data conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and used as the interface. Up to now, the conventional ADCs based on Nyquist sampling theorem are facing a critical challenge: the resolution and the sampling rate must be radically increased when some applications such as radar detection and ultra-wideband communication emerge. The offset of comparators and the setup time of sample-and-hold circuits, however, limit the resulution and clock rate of ADCs. Alternatively, in some applications such as speech, temperature sensor, etc. signals remain possibly unchanged for prolonged periods with brief bursts of significant activity. If trational ADCs are employed in such circumstances a higher bandwidth is required for transmitting the converted samples. On the other hand, sampling signals with an extremely high clock rate are also required for converting the signals with the feature of sparsity in time domain. The level-crossing sampling scheme (LCSS) is one of the data conversions suitable for converting signals with the sparsity feature and brief bursts of signigicant activity. due to the traditional LCSS with a fixed clock rate being limited in applications a novel irregular data conversion scheme called analogue-to-information system (AIS) is proposed in this thesis. The AIS is typically based upon LCSS, but an adjustable clock generator and a real time data compression scheme are applied to it. As the system-level simulations results of AIS show it can be seen that a data transmission saving rate nearly 30% is achieved for different signals. PLLs with fast pull-in and locking schemes are very important when they are applied in TDMA systems and fequency hopping wireless systems. So a novel triple path nonlinear phase frequency detector (TPNPFD) is also proposed in this thesis. Compared to otherPFDs, the pll-in and locking time in TPNPFD is much shorter. A proper transmission data format can make the recreation of the skipped samples and the reconstruction of the original signal more efficient, i.e. they can be achieved in a minimum number of the received data without increasing much more hardware complexity. So the preliminary data format used for transmitting the converted data from AIS is also given in the final chapter of this thesis for future works.

<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.</p><p>Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.</p><p>Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.</p><p>HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.</p>

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof¡¦s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 £gm CMOS process, and make a discussion on the testing performance of the PLL IC.