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A study of design methodologies for fault tolerant state machine controllersChalmers, Stewart John January 2000 (has links)
No description available.
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Design of Low-Power Controller-Datapath Systems Using FSM State Assignment and Output EncodingLiang, Jhih-Yuan 14 August 2007 (has links)
In large controller-datapath systems, the switching activity of datapath is administered by controller. The unnecessary switching activity will cause more power consumption, and therefore the design of controllers (i.e. Finite State Machines, FSMs) will influence the whole power consumption of the systems. The state assignment and output encoding are the two major factors influencing the power of system under the hardware implementation of controllers. In this paper, we present an integer linear programming (ILP) method to solve the state assignment and output encoding problems. The purpose is to reduce switching activity such that the goal of power optimization can be achieved. It has not to reschedule the operations of datapath under timing and resource constraints and has no extra area overhead. In order to verify the effectiveness of our proposed ILP approach, we use this approach to implement several controller-datapath systems. Experimental results show that our proposed approach achieves an average of 30.513% power savings compared to the traditional area optimal synthesis tool, SIS, where power is not considered. Our proposed approach does not cause extra area overhead while achieving a significant power saving of systems.
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Design of Low-Power Controllers for High-Performance Controller-Datapath SystemsLo, Mei-wei 24 July 2006 (has links)
The state assignment is one of the most important problems in hardware implementation of controllers (finite state machines, FSMs). Traditional heuristics include simulated annealing (SA), greedy approach, and recursive Min-Cut partitioning. Since these methods can¡¦t reduce both area and power, thus we propose a new approach which using integer linear programming (ILP) to solve the state assignment. The proposed of ILP approach can set the weight and reach best solution between less area and low power. The approach can find out the best state assignment for both low-area and low power consumption. In addition, we also use ILP to solve the output encoding of controller in order to reduce the power consumption of datapath.
Finally, to verify the effectiveness of our proposed approach, we do some experiments on several MCNC FSM benchmarks and controller-datapath systems. The experimental results show that a significant power and area savings can be achieved.
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Realisierung eines Verilog/VHDL Codegenerators fuer graphisch erfasste Finite State MachinesRoy, Diana 24 March 1997 (has links) (PDF)
Es wurden verschieden Kodierungsarten fuer FSMs untersucht,
schwerpunktmaessig Gray Code und andere Arten der hazardfreien
Kodierung.
Ein spezieller Kodierungsalgorithmus zur hazardfreien
Kodierung wurde entwickelt und in eine Entwurfsumgebung
implementiert.
Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die
eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL
erzeugen.
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Analyse von Schnittstellenkompatibilität von Steuergeräten auf Basis von MSC-BeschreibungenMa, Zheng 18 March 2008 (has links) (PDF)
In modernen Fahrzeugen befindet sich eine Vielzahl von Steuergeräten, die verschiedenste
Funktionen, wie z.B. das Antiblockiersystem (ABS) realisieren. Die Funktionalitäten
von Steuergeräten werden heute mit unterschiedlichen Methoden beschrieben. Eine
dieser Methoden sind Message Sequence Charts (MSCs). Aufgrund der Freiheitsgrade
von MSCs gibt es verschiedene Möglichkeiten gleiche Funktionalität unterschiedlich zu
beschreiben. In dieser Arbeit wird eine Methode definiert, wie verschiedene MSCs hinsichtlich
Funktionskompatibilität auf Basis von endlichen Automaten untersucht werden
können.
Diese Diplomarbeit ist in zwei Schwerpunkte gegliedert. Zum einen soll ein Konzept
für die Transformation des MSCs in der entsprechenden Automaten-Darstellung und einen
Vergleich-Algorithmus zur Rückwärtskompatibilitätsanalyse der endlichen Automaten entwickelt
werden. Zum anderen ist es Aufgabe, die Methode auf Basis von Java zu implementieren
und in die Software-Plattform CAMP zu integrieren.
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Improving fault coverage and minimising the cost of fault identification when testing from finite state machinesGuo, Qiang January 2006 (has links)
Software needs to be adequately tested in order to increase the confidence that the system being developed is reliable. However, testing is a complicated and expensive process. Formal specification based models such as finite state machines have been widely used in system modelling and testing. In this PhD thesis, we primarily investigate fault detection and identification when testing from finite state machines. The research in this thesis is mainly comprised of three topics - construction of multiple Unique Input/Output (UIO) sequences using Metaheuristic Optimisation Techniques (MOTs), the improved fault coverage by using robust Unique Input/Output Circuit (UIOC) sequences, and fault diagnosis when testing from finite state machines. In the studies of the construction of UIOs, a model is proposed where a fitness function is defined to guide the search for input sequences that are potentially UIOs. In the studies of the improved fault coverage, a new type of UIOCs is defined. Based upon the Rural Chinese Postman Algorithm (RCPA), a new approach is proposed for the construction of more robust test sequences. In the studies of fault diagnosis, heuristics are defined that attempt to lead to failures being observed in some shorter test sequences, which helps to reduce the cost of fault isolation and identification. The proposed approaches and techniques were evaluated with regard to a set of case studies, which provides experimental evidence for their efficacy.
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The Use of Contextual Clues in Reducing False Positives in an Efficient Vision-Based Head Gesture Recognition SystemBlonski, Brian M 01 June 2010 (has links) (PDF)
This thesis explores the use of head gesture recognition as an intuitive interface for computer interaction. This research presents a novel vision-based head gesture recognition system which utilizes contextual clues to reduce false positives. The system is used as a computer interface for answering dialog boxes. This work seeks to validate similar research, but focuses on using more efficient techniques using everyday hardware. A survey of image processing techniques for recognizing and tracking facial features is presented along with a comparison of several methods for tracking and identifying gestures over time. The design explains an efficient reusable head gesture recognition system using efficient lightweight algorithms to minimize resource utilization. The research conducted consists of a comparison between the base gesture recognition system and an optimized system that uses contextual clues to reduce false positives. The results confirm that simple contextual clues can lead to a significant reduction of false positives. The head gesture recognition system achieves an overall accuracy of 96% using contextual clues and significantly reduces false positives. In addition, the results from a usability study are presented showing that head gesture recognition is considered an intuitive interface and desirable above conventional input for answering dialog boxes. By providing the detailed design and architecture of a head gesture recognition system using efficient techniques and simple hardware, this thesis demonstrates the feasibility of implementing head gesture recognition as an intuitive form of interaction using preexisting infrastructure, and also provides evidence that such a system is desirable.
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Génération automatique de cas de test pour les systèmes modélisés par des machines à états finis communicantesBourhfir, Chourouk January 1999 (has links)
Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal.
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LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMSTIWARI, ANURAG 31 May 2005 (has links)
No description available.
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LOW POWER CONTROLLER MAPPING BY DISABLING THE EMBEDDED MEMORY BLOCKS IN FPGAsJANARTHANAN, ARUN 02 July 2007 (has links)
No description available.
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