International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / A switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.

<p>0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. </p><p>This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). </p><p>Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell. </p><p>The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products. </p><p>In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.</p>

0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell. The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products. In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.

The notion of mechanical computation has been revived in the past few years, with the advances of nanofabrication techniques. Although electromechanical devices are inherently slow, they offer zero or very low off-state current, which reduces the overall power consumption compared to the fast complementary-metal-oxide-semiconductor (CMOS) counterparts. This energy efficiency feature is the most crucial requirement for most of the stand-alone battery-operated gadgets, biomedical devices, and the internet of things (IoT) applications, which do not require the fast processing speeds offered by the mainstream CMOS technology. In particular, using Micro-Electro-Mechanical (MEM) resonators in mechanical computing has drawn the attention of the research community and the industry in the last decade as this technology offers low power consumption, reduced circuit complexity compared to conventional CMOS designs, run-time re- programmability and high reliability due to the contactless mode of operation compared to other MEM switches such as micro-relays. In this thesis, we introduce digital circuit design techniques tailored for clamped-clamped beam MEM resonators. The main operation mechanism of these circuit blocks is based on fine-tuning of the resonance frequency of the micro-resonator beam, and the logic function performed by the devices is mainly determined by factors such as input/output terminal arrangement, signal type, resonator operation regime (linear/non-linear), and the operation frequency. These proposed circuits include the major building blocks of any microprocessor such as logic gates, a full adder which is a key block in any arithmetic and logic operation units (ALU), and I/O interface units, including digital to analog (DAC) and analog to digital (ADC) data converters. All proposed designs were first simulated using a finite element software and then the results were experimentally verified. Important aspects such as energy per operation, speed, and circuit complexity are evaluated and compared to CMOS counterparts. In all applications, we show that by proper scaling of the resonator’s dimensions, MHz operation speeds and energy consumption in the range of femto-joules per logic operation are attainable. Finally, we discuss some of the challenges in using MEM resonators in digital circuit design at the device level and circuit level and propose solutions to tackle some of them.

<p>Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well.</p><p>In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources.</p><p>In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations.</p><p>The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs.</p><p>Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.</p>

Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well. In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources. In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations. The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs. Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.

No description available.