Threshold logic gates have the capability of realizing complex Boolean functions with smaller number of logic gates [1]. These gates are very sensitive to their weight values which may change during manufacturing process. So Threshold logic gates should be carefully designed to allow for maximum deviation from desired design weight values without affecting its functionality . This maximum allowable deviation is known as Fault Tolerance of the gate. ILP is one of the methods to find the optimum weight values with fault tolerance. But ILP has inability to solve the threshold functions with large inputs. This thesis presents two methods to overcome this difficulty.First one is the Combination method which combines the procedures of both decomposition method and ILP method .Second one is the Variable collapsing method which uses the principle of Variable Collapsing to find weights values with fault tolerance for large input functions.

Due to the low current ratings of the currently available silicon carbide (SiC) switches they cannot be employed in high-power converters. Thus, it is necessary to parallel-connect several switches in order to reach higher current ratings. This paper presents an investigation of parallel-connected normally-on SiC junction field effect transistors. There are four crucial parameters affecting the effectiveness of the parallel-connected switches. However, the pinch-off voltage and the reverse breakdown voltage of the gates seem to be the most important parameters which affect the switching performance of the devices. In particular, the spread in these two parameters might affect the stable off-state operation of the switches. The switching performance and the switching losses of a pair of parallel-connected devices having different reverse breakdown voltages of the gates is investigated by employing three different gate-driver configurations. It is experimentally shown that using a single gate-driver circuit the switching performance of the parallel-connected devices is almost identical, while the total switching losses are lower compared to the other two configurations. / <p>QC 20121116</p>

Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.

Logic gates are the fundamental building blocks of digital circuits. In this episode, we take a look at the four most basic gates: AND, OR, exclusive-OR, and the inverter, and show how an XOR gate can be used to compare two digital values. Click here to read the show transcript.

DNA nanotechnology has been developed in order to construct nanostructures and nanomachines by virtue of the programmable self-assembly properties of DNA molecules. Although DNA nanotechnology initially focused on spatial arrangement of DNA strands, new horizons have been explored owing to the development of the toehold-mediated strand-displacement reaction, conferring new dynamic properties to previously static and rigid structures. A large variety of DNA reconfigurable nanostructures, stepped and autonomous nanomachines and circuits have been operated using the strand-displacement reaction. Biological systems rely on information processing to guide their behaviour and functions. Molecular computation is a branch of DNA nanotechnology that aims to construct and operate programmable computing devices made out of DNA that could interact in a biological context. Similar to conventional computers, the computational processes involved are based on Boolean logic, a propositional language that describes statements as being true or false while connecting them with logic operators. Numerous logic gates and circuits have been built with DNA that demonstrate information processing at the molecular level. However, development of new systems is called for in order to perform new tasks of higher computational complexity and enhanced reliability. The contribution of secondary structure to the vulnerability of a toehold-sequestered device to undesired triggering of inputs was examined, giving new approaches for minimizing leakage of DNA devices. This device was then integrated as a logic component in a DNA-based computer with a retrievable memory, thus implementing two essential biological functions in one synthetic device. Additionally, G-quadruplex logic gates were developed that can be switched between two topological states in a logic fashion. Their individual responses were detected simultaneously, establishing a new approach for parallel biological computing. A new AND-NOT logic circuit based on the seesaw mechanism was constructed that, in combination with the already existing AND and OR gates, form a now complete basis set that could perform any Boolean computation. This work introduces a new mode of kinetic control over the operation of such DNA circuits. Finally, the first example of a transmembrane logic gate being operated at the single-molecule level is described. This could be used as a potential platform for biosensing.

The present work consists of three parts. In the first part (chapters III and IV), the dynamics of Lorentz lattice gases (LLG) on graphs is analyzed. We study the fixed scatterer model on finite graphs. A tight bound is established on the size of the orbit for arbitrary graphs, and the model is shown to perform a depth-first search on trees. Rigidity models on trees are also considered, and the size of the resulting orbit is established. In the second part (chapter V), we give a complete description of dynamics for LLG on the one-dimensional integer lattice, with a particular interest in showing that these models are not capable of universal computation. Some statistical properties of these models are also analyzed. In the third part (chapter VI) we attempt to partition a pool of workers into teams that will function as independent TSS lines. Such partitioning may be aimed to make sure that all groups work at approximately the same rate. Alternatively, we may seek to maximize the rate of convergence of the corresponding dynamical systems to their fixed points with optimal production at the fastest rate. The first problem is shown to be NP-hard. For the second problem, a solution for splitting into pairs is given, and it is also shown that this solution is not valid for partitioning into teams composed of more than two workers.

ABSTRACT TOWARDS PRACTICAL APPLICATIONS FOR MOLECULAR LOGIC GATES: &ldquo / AND&rdquo / LOGIC AS AN ADDITIONAL LAYER OF SELECTIVITY IN SINGLET OXYGEN RELEASE FOR PHOTODYNAMIC THERAPY &Ouml / zlem, Suriye M.S., Department of Chemistry Supervisor: Prof. Dr. Engin Umut Akkaya June 2008, 54 pages There have been many examples of individual molecular logic gates and molecular equivalents of more complex digital designs in recent years such as half adder, half subtractor, multiplexer. Neverethless, the unresolved issues of addressability and lack of communication between logic gates remain to be the Achille&rsquo / s heel for molecular logic gates. A few years ago we have demonstrated that appropriately decorated bodipy dyes can be very efficient generators for singlet oxygen, thus act as a satisfactory photodynamic agents. As a bonus, these dyes absorb very strongly at 660 nm which is considered to be within the therapeutic window of mammalian tissue. So, combining our earlier experience in molecular logic gates and rational design of photodynamic agents, we proposed a photodynamic therapy agent that would release singlet oxygen at a much larger rate when the cancer related cellular parameters are above a threshold value at the same location. Following the survey of the relevant literature for cancer related parameters, we decided that sodium ion concentration and pH (H+ concentration) could be very promising targets. In the tumor regions the pH can drop below 6 and the Na+ concentration is also significantly higher then normal tissues. As a result, in the proposed logic system the chemical inputs could be Na+ and H+. The system in fact is an automaton which is to seek higher concentration of both hydrogen and sodium ions, and release the toxic agent (singlet oxygen) only when both concentrations are high. Thus, the proposed logic gate is an AND logic gate, the output of which is singlet oxygen. Keywords: Photodynamic therapy, singlet oxygen, molecular logic gates, AND logic operation

Recent trend of minimization in microprocessors has introduced increasing self-heating effects in FinFET and MOSFET transistors. To study these self-heating effects, we developed self-consistent 3D models of FinFET and MOSFET basic logic gates, and simulated steady-state thermal transport for the worst heating case scenario. Incorporating size-dependent effective thermal conductivity of thin films instead of bulk values, these simulations provide a more accurate prediction of temperature rise in the logic gates. Results of our simulations predict higher temperature rise in FinFETs, compared to MOSFETs. Existence of buried oxide layer and confined geometry of FinFET structure are determined to be the most contributing to this higher temperature rise. To connect the results of our simulations to higher scale simulations, we proposed an equivalent thermal conductivity for each basic logic gate. These values were tested and found to be independent of the magnitude of chosen boundary conditions, as well as heat generation rate.

Recent trend of minimization in microprocessors has introduced increasing self-heating effects in FinFET and MOSFET transistors. To study these self-heating effects, we developed self-consistent 3D models of FinFET and MOSFET basic logic gates, and simulated steady-state thermal transport for the worst heating case scenario. Incorporating size-dependent effective thermal conductivity of thin films instead of bulk values, these simulations provide a more accurate prediction of temperature rise in the logic gates. Results of our simulations predict higher temperature rise in FinFETs, compared to MOSFETs. Existence of buried oxide layer and confined geometry of FinFET structure are determined to be the most contributing to this higher temperature rise. To connect the results of our simulations to higher scale simulations, we proposed an equivalent thermal conductivity for each basic logic gate. These values were tested and found to be independent of the magnitude of chosen boundary conditions, as well as heat generation rate.

A crescente evolução das tecnologias de fabricação de circuitos integrados demanda o desenvolvimento de novas ferramentas de CAD. O desenvolvimento tradicional de circuitos digitais a nível físico baseia-se em bibliotecas de células. Estas bibliotecas de células oferecem certa previsibilidade do comportamento elétrico do projeto devido à caracterização prévia das células. Além disto,diferentes versões para cada célula são requeridas de forma que características como atraso e consumo sejam atendidos, aumentando o número de células necessárias em uma bilioteca. A geração automática de leiautes é uma alternativa cada vez mais importante para a geracão baseada em células. Este método implementa transistores e conexões de acordo com padrões que são definidos em algoritmos sem as limitações impostas pelo uso de uma biblioteca de células. A previsibilidade em leiautes gerado automaticamente é oferecida por ferramentas de análise e estimativa. Estas ferramentas devem ser aptas a trabalhar com estimativas do leiaute e gerar informações relativas a atraso, potência e área. Este trabalho inclui a pesquisa de novos métodos de síntese física e a implementação de um gerador automático de leiautes cujas células são geradas no momento da síntese do leiaute. A pesquisa investiga diferentes estratégias de disposição dos componentes (transistores, contatos e conexões) em um leiaute e seus efeitos na ocupação de área e no atraso e de um circuito. A estratégia de leiaute utilizada aplica técnicas de otimização de atraso pela integração com uma técnicas de dimensionamento de transistores. Isto é feito de forma que o método de folding permita diferentes dimensionamentos para os transistores. As principais características da estratégia proposta neste trabalho são: linhas de alimentação entre bandas, roteamento sobre o leiaute (não são utilizados canais de roteamento) e geração de leiautes visando a redução do atraso do circuito pela aplicação da técnica de dimensionamento ao leiaute e redução do comprimento médio das conexões. O fato de permitir a implementação de qualquer combinação de equações lógicas, sem as restrições impostas pelo uso de uma biblioteca de células, permite a síntese de circuitos com uma otimização do número de transistores utilizados. Isto contribui para a diminuição de atrasos e do consumo, especialmente do consumo estático em circuitos submicrônicos. Comparações entre a estratégia proposta e outros métodos conhecidos são apresentadas de forma a validar a proposta apresentada. / The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.