This thesis describes the development of a gallium arsenide (GaAs) photocathode preparation facility (PPF) with a load-lock interface as part of an upgrade to the ALICE photo-injector electron gun. The PPF has the capacity to prepare up to six negative electron affinity (NEA) GaAs photocathodes, and permits the rapid and reliable replacement of the degraded photocathode in the gun, while maintaining the integrity of the gun vacuum system. The photocathode preparation has been studied and developed using a custum-built surface characterisation system which permitsthe preparation of NEA GaAs photocathode in conjunction with the application ofseveral surface science characterisation techniques within the same vacuum system. With GaAs/AlGaAs hetero-structure photocathodes designed and developed in collaboration with the Institute of Semiconductor Physics (ISP/Novosibirsk), quantum efficiencies (QE) of 15 - 19% at 635 nm and long lifetimes of the order of 6,800 hours are achieved in a reproducible way. Using the PPF, I have investigated the degradation in the QE of NEA GaAs photocathodes under exposures to gases typically present in the gun vacuum, namely O2, CO2, CO, H2, CH4 and N2. The effects of these gases on the NEA GaAs photocathodes have been demonstrated for the firrst time in a vacuum set-up with a base pressure in 10E-11 mbar range. It was found that H2, CH4 and N2 have no effect on the photocathodes lifetime, whilst substantial reductions of the QE have been observed during the exposures to O2, CO2 and CO. It was also demonstrated for the first time that the NEA GaAs photocathode activated with Cs and NF3 is more stable during CO2 and CO exposures than the photocathode activated with Cs and O2.

Thermoelectric devices (TEDs) are useful in a variety of niche applications, but low efficiencies limit their broader application. Semiconductor nanowires (NWs) could be the key to efficient thermoelectrics, through the benefits of one-dimensional band structures and a greatly reduced thermal conductivity. This thesis explores the transport fundamentals, experimental characterization, and computational approaches relevant to prospective III-V NW TEDs. Predictive electronic transport models are outlined for NWs and bulk III-Vs. These models are used to determine the optimum carrier concentration for maximizing the thermoelectric figure of merit (𝑍𝑇) in the bulk and in NWs of arbitrary size. We demonstrate the physical mechanisms underlying electronic thermoelectric improvements in NWs and confirm the superior performance of InSb and InAs, among other III-Vs. Next, thermal conductivity reduction in structurally complex NWs is investigated as a means of improving 𝑍𝑇. We compare polytypic and twinning superlattice (TSL) GaAs NWs in measurements obtained by a novel application of the 3𝜔 method. We find thermal conductivities of 8.4 ± 1.6 W/m-K and 5.2 ± 1.0 W/m-K for the polytypic and TSL NWs, respectively, demonstrating a significant difference and an almost ten-fold reduction compared to 50 W/m-K of bulk GaAs. We employ molecular dynamics simulations and the atomistic Green’s function method to address phonon engineering in generalized GaAs NW structures. In comparing twinning NWs, we find that a TSL period of 50 Å minimizes the lattice thermal conductivity across all the diameters considered. Our results also illustrate the importance of NW surfaces versus the internal crystal structure. Phonon coherence lengths are obtained by analyzing thermal conductivity trends in periodic and aperiodic structures. Transmission spectra are calculated to reveal the phonon frequencies targeted by structural engineering in NWs. These findings explain the range of thermal conductivities obtained for GaAs NWs with various crystal phases. Finally, to inform future growths of TSL NWs, we study the influence of the substrate temperature and V/III flux ratio on TSL formation in Te-doped GaAs NWs. The crystal structure of several NWs is investigated using transmission electron microscopy, revealing a range of polytypic and TSL morphologies. We find that periodic TSLs form only at low V/III flux ratios of 0.5 and substrate temperatures of 492 to 537 °C. To explain these trends, we derive a phase diagram for TSL NWs based on a kinetic growth model. / Thesis / Doctor of Philosophy (PhD) / In a circuit of dissimilar conductors, temperature differences create voltage differences that can drive electrical currents. Similarly, electrical currents in such circuits inherently lead to heating and cooling. These phenomena are known as thermoelectric effects because they couple heat and charge transport (electricity) in a symmetric and reversible way. The goal of some thermoelectric devices (TEDs) is to exploit these effects to generate electrical power or to provide controlled cooling. However, greater conversion efficiencies are required to compete against other existing technologies. With the advent of nanofabrication, semiconductor nanowires (NWs) have emerged as an attractive material system for efficient TEDs. In this thesis, we explore their thermal and electronic properties. We demonstrate a novel way to measure the NW thermal conductivity and employ computational methods to examine heat transport in NWs with various crystal structures. Finally, we examine how synthesis conditions can determine the morphology of NWs.

L’intégration monolithique de matériaux III-V ou Ge sur Si est un enjeu majeur de l’hétéroépitaxie qui a donné lieu à de nombreuses recherches depuis plus de vingt ans. Car premièrement, il permet de combiner des fonctionnalités optoélectroniques au standard industriel CMOS, cela peut remplacer des interconnexions métalliques par des interconnexions optiques dans lescircuits intégrés. De plus, le procédé d’intégration de semiconducteurs III-V ou de Ge sur Si permettrait de réduire sensiblement le coût de fabrication des cellules solaire pour le marché de niche du spatial.L’hétéroépitaxie directe de tels matériaux sur Si n’est pas aisée du fait du fort désaccord de maille et du différent coefficient de dilatation thermique entre ces matériaux. Plusieurs méthodes on tété proposées au cours des 20 derniers, notamment les solutions reposant sur des technologies de report telle que ‘Smart Cut TM’, ‘GEOI condensation’ donnent d’excellents résultats, mais n’offre pas autant de souplesse qu’une technologie d’hétéroépitaxie, et induit des coûts nettement supérieurs.L’objectif de cette thèse est de proposer une solution qui consiste à intégrer de façon monolithique des semiconducteurs III-V sur Si en utilisant des couches tampons des oxydes. Nous avons tout d’abord montré de manière théoriquement et expéritalement que pour les systèmes semiconducteur/oxyde, le semiconducteur croît avec son paramètre de maille massif dès le début decroissance et ne contient pas de défaut entendus associé à la relaxation plastique, la différence deparamètre de maille est entièrement accommodée par un réseau de dislocation interfacial. Il est donc apriori possible d’obtenir une couche 2D plane de semiconducteur/oxyde par la coalescence des îlots sans défauts étendus, présentant le paramètre de maille massif du semiconducteur dès le début de lacroissance, a condition qu’aucun défaut ne soit formé lors de la coalescence des îlots.La deuxième partie est dédiée à la coalescence des îlots pour le système InP/SrTiO3/Si, une stratégie de 3-étape a été utilisé pour favoriser la coalescence des îlots InP sur SrTiO3, la couche InPcoalescée présente une très bonne qualité structurale et surfacique. Cependant, nous avons observé la présence de défauts, notamment des micromacles et des parois d’inversion. Malgré ses défauts dans la couche, nous avons réalisé le puits quantique InP/InAsP épitaxié sur SrTiO3/Si, il présente une meilleure qualité cristalline et optique comparé avec un puits quantique référence InP/InAsP qui est épitaxié directement sur Si. / The monolithic integration of III-V semiconductors and Ge on Si is a major issue of heteroepitaxy that gave rise to extensive researches for over twenty years. Firstly because it allows combining the optoelectronic functionalities with industry standard CMOS, which can replace the metal interconnects by optical interconnects in integrated circuits. Moreover, the integration of III-V semiconductors or Ge on Si would significantly reduce the manufacturing cost of solar cells for the niche space market.The direct heteroepitaxy of III-V semiconductor on Si is difficult because of the great lattice mismatch and different thermal expansion coefficient between these materials. Various methods have been proposed in the last twenty years, especially, the solutions based on sticking technologies such as‘Smart Cut TM’ offer excellent results, but is limited by its less flexibility and higher cost.The objective of this thesis is to propose a solution that consists in integrating monolithicallyIII-V semiconductors on Si by using the buffer layers of oxides. We have firstly demonstrated theoretically and experimentally that for the systems semiconductor/oxide, the semiconductor grows with his lattice parameter from the beginning of the growth and doesn’t contain any defaults associated with the plastic relaxation, the difference of the lattice parameter is fully accommodated bythe interfacial dislocations, thus, it’s a priori possible to obtain a flat 2D layer of semiconductor/oxideby the coalescence of the islands without extended defects, presenting the lattice parameter of the semiconductor from the beginning of the growth, providing that no defect is formed during the coalescence of islands.The second part is dedicated to the coalescence of islands for the system InP/SrTiO3/Si, a 3-step strategy was used to favor the coalescence of islands InP on SrTiO3/Si, the coalesced InP layershows good crystalline quality and excellent surface quality. However, we observed the presence of defects, including anti-phase boundaries and microtwins. Despite these defects in the layer, we have realized a quantum well InP/InAsP grown on SrTiO3/Si, it presents a better quality crystal and optical compared with a reference quantum well InP/InAsP that grows directly on Si.

[pt] Este trabalho apresenta sistemáticas para projetos de osciladores de microondas empregando basicamente como elemento ativo o transistor FET GaAs em várias configurações. Inicialmente o modelamento a pequenos sinais é estudado e um projeto é desenvolvido para comprovação experimental. Determinações de redes adaptadoras de saídas para o oscilador são apresentadas. A teoria básica de osciladores de microondas a resistência negativa é mostrada com o intuito de modelar o dispositivo ativo em nível de grandes sinais. Um estudo de ruído em osciladores de microondas também é desenvolvido para uma melhor caracterização dos osciladores. Osciladores de microondas estabilizados a ressoadores dielétricos são estudados e um projeto numa configuração original é realizado. Programas Auxiliares de Projetos (PAP) prórpios para calculadoras programáveis de mesa foram desenvolvidos e testados nos projetos apresentados. / [en] In this work some methods of designing microwave oscillators, using GaAs FET`s as the active device, are presented. First, the small-signal is discussed and a pratical circuit is shown . the role of the outpu matching structures is pointed out. The basic theory of negative-resistance microwave oscillator is presented as a tool for the large signal modeling. Noise-effect on the performance of the whole device is also studied. An original contribution on stabilyzed dielectric resonator oscillator is given since a new configuration is suggested. This work was heavily supported by a powerful software that enables computer aided design facilities.

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This thesis documents a study of bonding stress and the reliability of GaAs-based lasers for high-power applications. GaAs-based lasers were bonded to oxygen-free high- conductivity (OFHC) copper heat sinks using a eutectic PbSn solder or a silver-filled conductive epoxy, and life tested. Epoxy-bonded devices were observed to have a larger failure rate on life test than solder-bonded devices. Bonding stress, as measured by the degree of polarization (DOP) of photoluminescence, was found to be the largest in epoxy-bonded devices. As well, the type of heat sink and bonding adhesive affected the stress in the laser material, with bonding stress increasing when there was a larger mismatch of coefficients of thermal expansion between the laser material, adhesive and heat sink. The reliability of the lasers was affected by the amount of force applied to unbonded laser chips. As the applied force increased on a chip centred on a groove, the rate of degradation in the output power increased. A limit in stress tolerance was observed in the lasers, which meant that larger amounts of stress would lead to increased rates of degradation in the output power. As well, the performance of lasers selected from a batch showing poor reliability degraded at an accelerated rate after several hours of operation under applied strain. / Thesis / Master of Engineering (ME)

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