Redes Neurais têm sido um tema de pesquisas por pelo menos sessenta anos. Desde a eficácia no processamento de informações à incrível capacidade de tolerar falhas, são incontáveis os mecanismos no cérebro que nos fascinam. Assim, não é nenhuma surpresa que, na medida que tecnologias facilitadoras tornam-se disponíveis, cientistas e engenheiros têm aumentado os esforços para o compreender e simular. Em uma abordagem semelhante à do Projeto Genoma Humano, a busca por tecnologias inovadoras na área deu origem a projetos internacionais que custam bilhões de dólares, o que alguns denominam o despertar global de pesquisa da neurociência. Avanços em hardware fizeram a simulação de milhões ou até bilhões de neurônios possível. No entanto, as abordagens existentes ainda não são capazes de fornecer a densidade de conexões necessária ao enorme número de neurônios e sinapses. Neste sentido, este trabalho propõe DHyANA (Arquitetura Digital Neuromórfica Hierárquica), uma nova arquitetura em hardware para redes neurais pulsadas, a qual utiliza comunicação em rede-em-chip hierárquica. A arquitetura é otimizada para implementações de Máquinas de Estado Líquido. A arquitetura DHyANA foi exaustivamente testada em plataformas de simulação, bem como implementada em uma FPGA Stratix IV da Altera. Além disso, foi realizada a síntese lógica em tecnologia 65nm, a fim de melhor avaliar e comparar o sistema resultante com projetos similares, alcançando uma área de 0,23mm2 e potência de 147mW para uma implementação de 256 neurônios. / Neural Networks has been a subject of research for at least sixty years. From the effectiveness in processing information to the amazing ability of tolerating faults, there are countless processing mechanisms in the brain that fascinates us. Thereupon, it comes with no surprise that as enabling technologies have become available, scientists and engineers have raised the efforts to understand, simulate and mimic parts of it. In a similar approach to that of the Human Genome Project, the quest for innovative technologies within the field has given birth to billion dollar projects and global efforts, what some call a global blossom of neuroscience research. Advances in hardware have made the simulation of millions or even billions of neurons possible. However, existing approaches cannot yet provide the even more dense interconnect for the massive number of neurons and synapses required. In this regard, this work proposes DHyANA (Digital HierArchical Neuromorphic Architecture), a new hardware architecture for a spiking neural network using hierarchical network-on-chip communication. The architecture is optimized for Liquid State Machine (LSM) implementations. DHyANA was exhaustively tested in simulation platforms, as well as implemented in an Altera Stratix IV FPGA. Furthermore, a logic synthesis analysis using 65-nm CMOS technology was performed in order to evaluate and better compare the resulting system with similar designs, achieving an area of 0.23mm2 and a power dissipation of 147mW for a 256 neurons implementation.

This thesis, presents a multiprocessor topology, the hierarchical network of hyper-cubes, which has a low diameter, low degree of connectivity and yet exhibits hypercube like versatile characteristics. The hierarchical network of hyper-cubes consists of k-cubes interconnected in two or more hierarchical levels. The network has a hierarchical, expansive, recursive structure with a constant pre-defined building block. The basic building block of the hierarchical network of hyper-cubes comprises of a k-cube of processor elements and a network controller. The hierarchical network of hyper-cubes retains the positive features of the k-cube at different levels of hierarchy and has been found to perform better than the binary hypercube in executing a variety of application problems. The ASCEND/DESCEND class of algorithms can be executed in O(log2 N) parallel steps (N is the number of data elements) on a hierarchical network of hypercubes with N processor elements. A description of the topology of the hierarchical network of hypercubes is presented and its architectural potential in terms of fault-tolerant message routing, executing a class of highly parallel algorithms, and in simulating artificial neural networks is analyzed. Further, the proposed topology is found to be very efficient in executing multinode broadcast and total exchange algorithms. We subsequently, propose an improvisation of the network to counter faults, and explore implementation of artificial neural networks to demonstrate efficient implementation of application problems on the network. The fault-tolerant capabilities of the hierarchical network of hypercubes with two network controllers per k-cube of processor elements are comparable to those of the hypercube and the folded hypercube. We also discuss various issues related to the suitability of multiprocessor architectures for simulating neural networks. Performance analysis of ring, hypercube, mesh and hierarchical network of hypercubes for simulating artificial neural networks is presented. Our studies reveal that the performance of the hierarchical network of hypercubes is better than those of ring, mesh, hypernet and hypercube topologies in implementing artificial neural networks. Design and implementation aspects of hierarchical network of hypercubes based on two schemes, viz., dual-ported RAM communication, and transputers are also presented. Results of simulation studies for robotic applications using neural network paradigms on the transputer-based hierarchical network of hypercubes reveal that the proposed network can produce fast response times of the order of hundred microseconds.

Redes Neurais têm sido um tema de pesquisas por pelo menos sessenta anos. Desde a eficácia no processamento de informações à incrível capacidade de tolerar falhas, são incontáveis os mecanismos no cérebro que nos fascinam. Assim, não é nenhuma surpresa que, na medida que tecnologias facilitadoras tornam-se disponíveis, cientistas e engenheiros têm aumentado os esforços para o compreender e simular. Em uma abordagem semelhante à do Projeto Genoma Humano, a busca por tecnologias inovadoras na área deu origem a projetos internacionais que custam bilhões de dólares, o que alguns denominam o despertar global de pesquisa da neurociência. Avanços em hardware fizeram a simulação de milhões ou até bilhões de neurônios possível. No entanto, as abordagens existentes ainda não são capazes de fornecer a densidade de conexões necessária ao enorme número de neurônios e sinapses. Neste sentido, este trabalho propõe DHyANA (Arquitetura Digital Neuromórfica Hierárquica), uma nova arquitetura em hardware para redes neurais pulsadas, a qual utiliza comunicação em rede-em-chip hierárquica. A arquitetura é otimizada para implementações de Máquinas de Estado Líquido. A arquitetura DHyANA foi exaustivamente testada em plataformas de simulação, bem como implementada em uma FPGA Stratix IV da Altera. Além disso, foi realizada a síntese lógica em tecnologia 65nm, a fim de melhor avaliar e comparar o sistema resultante com projetos similares, alcançando uma área de 0,23mm2 e potência de 147mW para uma implementação de 256 neurônios. / Neural Networks has been a subject of research for at least sixty years. From the effectiveness in processing information to the amazing ability of tolerating faults, there are countless processing mechanisms in the brain that fascinates us. Thereupon, it comes with no surprise that as enabling technologies have become available, scientists and engineers have raised the efforts to understand, simulate and mimic parts of it. In a similar approach to that of the Human Genome Project, the quest for innovative technologies within the field has given birth to billion dollar projects and global efforts, what some call a global blossom of neuroscience research. Advances in hardware have made the simulation of millions or even billions of neurons possible. However, existing approaches cannot yet provide the even more dense interconnect for the massive number of neurons and synapses required. In this regard, this work proposes DHyANA (Digital HierArchical Neuromorphic Architecture), a new hardware architecture for a spiking neural network using hierarchical network-on-chip communication. The architecture is optimized for Liquid State Machine (LSM) implementations. DHyANA was exhaustively tested in simulation platforms, as well as implemented in an Altera Stratix IV FPGA. Furthermore, a logic synthesis analysis using 65-nm CMOS technology was performed in order to evaluate and better compare the resulting system with similar designs, achieving an area of 0.23mm2 and a power dissipation of 147mW for a 256 neurons implementation.

Redes Neurais têm sido um tema de pesquisas por pelo menos sessenta anos. Desde a eficácia no processamento de informações à incrível capacidade de tolerar falhas, são incontáveis os mecanismos no cérebro que nos fascinam. Assim, não é nenhuma surpresa que, na medida que tecnologias facilitadoras tornam-se disponíveis, cientistas e engenheiros têm aumentado os esforços para o compreender e simular. Em uma abordagem semelhante à do Projeto Genoma Humano, a busca por tecnologias inovadoras na área deu origem a projetos internacionais que custam bilhões de dólares, o que alguns denominam o despertar global de pesquisa da neurociência. Avanços em hardware fizeram a simulação de milhões ou até bilhões de neurônios possível. No entanto, as abordagens existentes ainda não são capazes de fornecer a densidade de conexões necessária ao enorme número de neurônios e sinapses. Neste sentido, este trabalho propõe DHyANA (Arquitetura Digital Neuromórfica Hierárquica), uma nova arquitetura em hardware para redes neurais pulsadas, a qual utiliza comunicação em rede-em-chip hierárquica. A arquitetura é otimizada para implementações de Máquinas de Estado Líquido. A arquitetura DHyANA foi exaustivamente testada em plataformas de simulação, bem como implementada em uma FPGA Stratix IV da Altera. Além disso, foi realizada a síntese lógica em tecnologia 65nm, a fim de melhor avaliar e comparar o sistema resultante com projetos similares, alcançando uma área de 0,23mm2 e potência de 147mW para uma implementação de 256 neurônios. / Neural Networks has been a subject of research for at least sixty years. From the effectiveness in processing information to the amazing ability of tolerating faults, there are countless processing mechanisms in the brain that fascinates us. Thereupon, it comes with no surprise that as enabling technologies have become available, scientists and engineers have raised the efforts to understand, simulate and mimic parts of it. In a similar approach to that of the Human Genome Project, the quest for innovative technologies within the field has given birth to billion dollar projects and global efforts, what some call a global blossom of neuroscience research. Advances in hardware have made the simulation of millions or even billions of neurons possible. However, existing approaches cannot yet provide the even more dense interconnect for the massive number of neurons and synapses required. In this regard, this work proposes DHyANA (Digital HierArchical Neuromorphic Architecture), a new hardware architecture for a spiking neural network using hierarchical network-on-chip communication. The architecture is optimized for Liquid State Machine (LSM) implementations. DHyANA was exhaustively tested in simulation platforms, as well as implemented in an Altera Stratix IV FPGA. Furthermore, a logic synthesis analysis using 65-nm CMOS technology was performed in order to evaluate and better compare the resulting system with similar designs, achieving an area of 0.23mm2 and a power dissipation of 147mW for a 256 neurons implementation.

Abstract This thesis proposes cross-layer approaches which enable to improve energy efficiency of wireless sensor networks and wireless body area networks (WSN & WBAN). The focus is on the physical (PHY) and medium access control (MAC) layers of communication protocol stack and exploiting their interdependencies. In the analysis of the PHY and MAC layers, their relevant characteristics are taken into account, and cross-layer models are developed to study the effect of these layers on energy efficiency. In addition, cross-layer analysis is applied at the network level by addressing hierarchical networks' energy efficiency. The objective is to improve energy efficiency by taking into account that substantial modifications to current standards and techniques are not required to take advantage of the proposed methods. The studied scenarios of WSN take advantage of the wake-up radio (WUR). A generic WUR-based MAC (GWR-MAC) protocol with objective to improve energy efficiency by avoiding idle listening is proposed. First, the proposed cross-layer model is developed at a general level and applied to study the forward error correction (FEC) code rate selection effect on the length of the transmission period and energy efficiency in a star topology network. Then an energy efficiency model for intelligent hierarchical architecture based on GWR-MAC is proposed and performance comparison with a duty-cycle radio (DCR) approach is performed. Interactions between different layers' devices are taken into account, and the WUR and DCR approaches are compared as a function of event frequency. The third cross-layer model focuses on the effect of the FEC code rate and data packet payload length on the energy efficiency of the IEEE Std 802.15.6-based WBANs using IR-UWB PHY. The results acquired by using analytical modelling and simulations with the Matlab software clearly illustrates the potential energy gains that can be achieved with the proposed cross-layer approaches. The developed WUR-based MAC protocol, analytical models and achieved results can be exploited by other researchers in the WSN and WBAN field. The contribution of this thesis is also to stimulate further research on these timely topics and foster development of short-range communication, which has a crucial role in future converging networks such as the Internet of Things. / Tiivistelmä Tässä väitöskirjassa ehdotetaan protokollakerrosten välistä tietoa hyödyntäviä (cross-layer) lähestymistapoja, jotka mahdollistavat energiatehokkuuden parantamisen langattomissa sensori- ja kehoverkoissa. Työ kohdistuu fyysisen- ja kanavanhallintakerroksen välisen vuorovaikutuksen tutkimiseen. Fyysisen- ja kanavanhallintakerrosten analyysissä huomioidaan niiden tärkeimmät ominaisuudet ja tutkitaan kerrosten yhteistä energiatehokkuutta. Lisäksi kerrosten välistä analyysiä sovelletaan verkkotasolle tutkimalla hierarkkisen verkon energiatehokkuutta. Tavoitteena on energiatehokkuuden parantamisen mahdollistaminen siten, että merkittäviä muutoksia nykyisiin standardeihin ja tekniikoihin ei tarvitse tehdä hyödyntääkseen ehdotettuja menetelmiä. Tutkitut sensoriverkkoskenaariot hyödyntävät heräteradiota. Väitöskirjassa ehdotetaan geneerinen heräteradiopohjainen kanavanhallintaprotokolla (GWR-MAC), jolla parannetaan energiatehokkuutta vähentämällä turhaa kanavan kuuntelua. Kerrosten välinen malli kehitetään ensin yleisellä tasolla ja sen avulla tutkitaan virheenkorjauskoodisuhteen valinnan vaikutusta lähetysperiodin pituuteen ja energiatehokkuuteen tähtitopologiaan pohjautuvissa sensoriverkoissa. Sitten väitöskirjassa ehdotetaan energiatehokkuusmalli älykkäälle GWR-MAC -protokollaan perustuvalle hierarkkiselle arkkitehtuurille ja sen suorituskykyä vertaillaan toimintajaksoperiaatteella toimivaan lähestymistapaan. Eri kerroksilla olevien laitteiden väliset vuorovaikutukset huomioidaan heräteradio- ja toimintajaksoperiaatteella toimivien verkkojen suorituskykyvertailussa tapahtumatiheyden funktiona. Kolmas malli kohdistuu virheenkorjauskoodisuhteen ja datapaketin hyötykuorman pituuden energiatehokkuusvaikutuksen tutkimiseen IEEE 802.15.6 -standardiin perustuvissa langattomissa kehoverkoissa. Analyyttinen mallinnus ja Matlab-ohjelmiston avulla tuotetut simulointitulokset osoittavat selvästi energiatehokkuushyödyt, jotka saavutetaan ehdotettuja menetelmiä käyttämällä. Kehitetty GWR-MAC -protokolla, analyyttiset mallit ja tulokset ovat hyödynnettävissä sensori- ja kehoverkkotutkijoiden toimesta. Tämän väitöskirjan tavoitteena on myös näiden ajankohtaisten aiheiden jatkotutkimuksen stimulointi sekä lyhyen kantaman viestinnän kehityksen vauhdittaminen, sillä niillä on erittäin merkittävä rooli tulevaisuuden yhteen liittyvissä verkoissa, kuten esineiden ja asioiden Internetissä.