This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a framework that automatically generates random programs with user specified features. These programs are used to verify the correctness of the compiled hardware by comparing the hardware simulation results with the software execution results. This way, users can have a large number of benchmarks to test their algorithms for HLS without having to manually develop test programs. The tool also provides additional ways of analyzing performance of HLS tools. Rather than being a replacement, this technique should serve as a useful complement to existing manually constructed test suites. Together, they can provide more comprehensive verification and analysis for HLS tools.

Along with the development of VLSI technology and the trend of system-on-chip design, traditional high-level synthesis can not deal with relatively complexity of system-on-chip design. In order to achieve optimal resource allocation, meet its performance and power requirements, and reduce its design time, we need a high-level synthesis software dealing system-level behavior. In consideration of system complexity, we have proposed a high-level synthesis method that synthesis for the task-level grains in a system behavior. This method performs efficient task-level resource allocation, task binding and task scheduling to reach a system design that meets the low performance and power requirements with low implementation cost. We utilize simulated annealing technique to achieve its overall system optimization. We designed and implemented the software design of the task-level high-level synthesis method. In this research, the design consists of three modules: the initial synthesis module, the heuristic movement module and the performance evaluation module. We will use the software to carry out the experiments of the task-level high-level synthesis method on application systems to verify its capability in designing systematic chips.

This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a framework that automatically generates random programs with user specified features. These programs are used to verify the correctness of the compiled hardware by comparing the hardware simulation results with the software execution results. This way, users can have a large number of benchmarks to test their algorithms for HLS without having to manually develop test programs. The tool also provides additional ways of analyzing performance of HLS tools. Rather than being a replacement, this technique should serve as a useful complement to existing manually constructed test suites. Together, they can provide more comprehensive verification and analysis for HLS tools.

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In this dissertation, the design and analysis of several fast arithmetic components are presented. Our contributions focus on the fast CORDIC rotation architectures and multipliers. In the CORDIC design, we proposed a fast rotation architecture that can reduce by half the average number of rotations. Furthermore, a new parallel CORDIC rotation algorithm and architecture (called para-CORDIC) is proposed that leads to smaller area and delay compared with the conventional CORDIC algorithm and previous works. In the design of the multiplier generator, a delay-efficient algorithm is used to perform the partial products summation and the final addition during the synthesis of fast parallel multipliers based on standard cell library or other full-custom circuit components. In the field of fixed-width multiplier designs, a lower-error fixed-width carry-free multiplier with low-cost compensation circuits is proposed that has smaller absolute average errors and variances compared with pervious methods.

Design Space Exploration is the task of identifying optimal implementation architectures for an application. On the front-end, it involves multi-objective optimization through a large space of options, and lends itself to a multitude of algorithmic approaches. On the back-end, it relies extensively on common capabilities such as model refinement, simulation and assessment of parameters like performance and cost. These characteristics present an opportunity to create an infrastructure that enables multiple approaches to be deployed using generic back-end services. In this work, we describe such a framework, developed using the System-on-Chip Environment, and we demonstrate the benefits and feasibility of deploying a variety of design space exploration approaches built on top of this basic infrastructure. / text

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This thesis is concerned with the development of a novel discrete particle swarm optimization (PSO) technique and its application to the discrete optimization of digital filter frequency response characteristics on the one hand, and the high-level synthesis of bit-parallel digital filter data-paths on the other. Two different techniques are presented for the optimization of sharp-transition band frequency response masking (FRM) digital filters, one of which is based on the conventional finite impulse-response (FIR) digital subfilters, and a new hardware-efficient approach which is based on utilizing infinite impulse-response (IIR) digital subfilters. It is shown that further hardware efficiency can be achieved by realizing the IIR interpolation subfilters by using the bilinear-LDI approach. The corresponding discrete PSO is carried out over the canonical signed digit (CSD) multiplier coefficient space for direct mapping to digital hardware considering simultaneous magnitude and group-delay frequency response characteristics. A powerful encoding scheme is developed for the high-level synthesis of digital filters based on discrete PSO, which preserves the data dependency relationships in the digital filter data-paths. In addition, a constrained discrete PSO is developed to overcome the limitations which would manifest themselves if the conventional PSO were to be used. Several examples are presented to demonstrate the application of discrete PSO to the design, high-level synthesis and optimization of digital filters. / Communications

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