Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region.  This thesis presents an experimental investigation on the GBTs as well as integration process developments for the fabrication of graphene-based devices. In this work, a full device fabrication and graphene integration process were designed with high CMOS compatibility considerations. To this aim, basic process modules, such as graphene transfer, deposition of materials on graphene, and formation of tunnel barriers, were developed and optimized. A PDMS-supporting graphene transfer process were introduced to facilitate the wet/dry wafer-scale transfer from metal substrate onto an arbitrarily substrate. In addition, dielectric deposition on graphene using atomic layer deposition (ALD) was investigated. These dielectric layers, mainly, served as the base-collector insulators in the fabricated GBTs. Moreover, the integration of silicon (Si) on the graphene surface was studied. Using the developed fabrication process, the first proof of concept devices were demonstrated. These devices utilized 5 nm-thick silicon oxide (SiO2) and about 20 nm-thick aluminum oxide (Al2O3) as the emitter-base insulator (EBI) and base-collector insulator (BCI). The direct current (DC) functionality of these devices exhibited &gt;104 on/off current ratios and a current transfer ratio of about 6%. The performance of these devices was limited by the non-optimized barrier parameters and device manufacturing technology. The possibility to improve and optimize the GBT performance was demonstrated by applying different barrier optimization approaches. Comparing to the proof of concept devices, several orders of magnitude higher injection current density was achieved using a bilayer dielectric tunnel barrier. Utilizing the novel TmSiO/TiO2 (1 nm/6 nm) dielectric stack, this tunnel barrier prevents defect mediated tunneling and, simultaneously, promotes the Fowler-Nordheim tunneling (FNT) and step tunneling (ST). Furthermore, it was shown that Si/graphene Schottky junction can significantly improve the current gain by reducing the electron backscattering at the base-collector barrier. In this thesis, a maximum current transfer ratio of about 35% has been achieved. / <p>QC 20160503</p>

Transistor Quantique InAs à Electrons Chauds: Fabrication submicronique et étude à haute fréquenceL'objectif de cette thèse est le développement de la technologie d'un transistor à électrons chauds constitué d'une hétérostructure quantique InAs/AlSb et exploitant un transport électronique résonant ultrarapide, le QHET (Quantum Hot Electron Transistor). Ce travail a permis l'étude approfondie de ses propriétés et performances à haute fréquence. L'étude aborde tous les aspects, de la conception, la croissance épitaxiale, la technologie de fabrication à la caractérisation statique et dynamique. Ce travail de thèse s'est effectué principalement à l'Institut d'Electronique du Sud (IES), sous la direction de Roland Teissier, et pour partie à l'Institut d'Electronique de Microélectronique et Nanotechnologie (IEMN) sous la direction de Mohamed Zaknoune. Nous avons, dans premier temps, mis en œuvre à l'IES une technologie double mésa afin de fabriquer les transistors avec l'émetteur de 10x10µm². La technologie en grande dimension est aisément réalisable et surtout reproductible. Elle nous a permis de travailler sur un grand nombre de structures transistor fabriquées par epitaxie par jets moléculaires (EJM) sur substrats InAs, afin d'en étudier le transport électronique et d'optimiser leur dessin. Le premier résultat marquant a été d'augmenter le gain statique jusqu'à une valeur de 15 grâce à une modification de la structure de l'émetteur qui une injection plus efficace puis l'utilisation d'une base fine de 85Å, qui améliore le temps de transit. Dans un deuxième temps, nous avons travaillé au sein de l'IES sur l'évolution de la technologie vers des dimensions intermédiaires dont la dimension la plus petite est de 1 µm de largeur. Cette technologie nous a donné une amélioration de performance des QHET grâce à la réduction des résistances et des capacités parasites des composants. Nous avons aussi travaillé à l'IEMN pour développer une technologie submicronique qui permet d'atteindre une largeur d'émetteur de 0.3 µm grâce à l'utilisation de la lithographie électronique. Cette technologie de fabrication plus performante nous a permis de mieux comprendre le fonctionnement du QHET. Et d'atteindre une régime de fonctionnement à forte densité de courant jusqu'à près de 1MA/ cm². Enfin, nous avons développé la structure et la technologie qui vont nous permettre d'évaluer la réponse à haute fréquence des QHET. Un point important a été de à disposer de la structure active du transistor sur un substrat isolant qui permette de réduire les éléments parasites durant la mesure en fréquence. Nous avons développé deux solutions : le transfert de substrat et la croissance métamorphique directement sur un substrat GaAs isolant.Les composants fabriqués par transfert de susbtrat présentent des valeurs de fréquence de transition FT de 77GHz et de fréquence d'oscillation FMAX de 88GHz. Les échantillons métamorphiques ont démontré de meilleures performances avec un FT de 170GHz et un FMAX supérieur à 200GHz. Ces résultats constituent les meilleurs dynamiques de transistors à électrons chauds à température ambiante. Ces études ont également fait progresser la compréhension du transport à haute fréquence dans ces composants. Ils permettent de comprendre les limitations actuelles et de proposer des pistes d'amélioration. / This work aims to develop a new high speed transistor in a vertical transport configuration that exploits the favourable transport properties of III-V semiconductor heterostructures based on InAs. This transistor is similar to a heterojunction bipolar transistor (HBT), but has theoretical assets to overcome the fundamental high speed limits of electron transport in HBT. Our approach uses the concept of hot electron transistor in an original InAs/AlSb quantum heterostructure, that we called a quantum hot electron transistor (QHET) or quantum cascade transistor (QCT). This research was almost done in Southern Electronics Institute (IES) under supervision of Dr. Roland Teissier and other work was realized in Micro-Nanotechnology Electronics Institute (IEMN) under supervision of Dr. Mohamed Zaknoune. The QHET is a unipolar vertical transport device made of a InAs/AlSb quantum heterostructure. Its first advantage over npn HBTs is the low base sheet resistance of 250 Ω/□ , accessible with moderate n-type doping levels (typically 1018 cm-3), which is a key parameter for high speed operation. Secondly, electron transport in the short (typically 100nm) bulk InAs collector is mostly ballistic with calculated transit times much shorter than in InP-based devices. We already developed the design and technology of QHET and demonstrated its resonant transports at cryogenic temperature and its improved static operation in smaller device. From these results, we come to develop our QHET structures to achieve high current gain. Using quantum design of thin base, the current gain is about 15. We fabricated QHET with emitter width scaled down to 0.3µm, using a state of the art electron beam lithography process. The junctions are defined using selective chemical etching. The base contact is self-aligned on the emitter contact. We achieved base resistance lower than 50Ω, comparable to state of the art HBTs. The small dimension allowed reaching the high current density regime of up to 1 MA/cm² required for high frequency operation. The static current gain is about 10, but could be increased up to 14 using a new quantum design. The collector breakdown voltage is greater than 1.2 V.Towards high frequency measurement, the substrate must be non-conducting material but InAs substrate is not available. Two technologies were proposed: transferred substrate and metamorphic substrate. For transferred substrate technology, we obtained a response of cutoff frequency of 77 GHz for FT and 88 for FMAX. For metamorphic substrate technology, we performed the growth of the transistor structures on a semi-insulating GaAs substrate. We used a thin GaSb buffer layer for metamorphic growth of the active part of the transistor, with an adequate growth procedure that allows forming mainly 90° misfit dislocations at the interface between the GaAs and GaSb. This technique permits more convenient and reliable processing of the devices, as compared to use of the more standard AlSb thick buffer layer. The frequency response was determined from S-parameters measured with a network analyser up to a frequency of 70 GHz. The measured gains, after de-embedding of the connection parasitic for a device with 0.5x4µm² emitter for JC=350kA/cm² (Ic= 6.0mA, Ib= 0.7mA, Vce=1.3V). The frequency dependence is not conventional on this device, with a resonance in the current gain close to 10 GHz and a slope different from -20 dB/decade for Mason's unilateral gains. Nevertheless, we could extract the cut-off frequencies FT=172 GHz from H21 and FMAX =230 GHz using -20dB/decade extrapolation of maximum stable gain (MSG). The present results confirmed the validity of this novel device concept. In addition, this is the first demonstration of the ability of a hot electron transistor to operate at high frequency at room temperature.