This work is a study of a hybrid adaptive controller that blends fixed feedback control and adaptive feedback control techniques. This type of adaptive controller removes the requirement that information about the disturbance is known apriori. Additionally, the control structure is implemented in such a way that as long as the adaptive controller is stable during adaptation, the system consisting of the controller and plant remain stable. The objective is to design and implement an adaptive controller that damps the structural vibrations induced in a multi-modal structure. The adaptive controller utilizes an adaptive infinite impulse response lattice filter for improved damping over the fixed feedback controller alone. An adaptive finite impulse response LMS filter is also implemented for comparison of the ability for both algorithms to reject harmonic, narrow bandwidth and wide bandwidth disturbances. It is demonstrated that the lattice filter algorithm performs slightly better than the LMS filter algorithm in all three disturbance cases. The lattice filter also requires less than half the order of the LMS filter to get the same performance. / Master of Science

Digital Signal Processing(DSP) algorithms are widely implemented in real time systems.In fields such as digital music technology, many of these said algorithms areimplemented, often in combination, to achieve the desired functionality. When itcomes to implementation, DSP algorithms are performance critical as they havetight deadlines. In this thesis, performance optimization using Single InstructionMultiple Data(SIMD) vectorization technique is performed on the ARM Cortex-A15 architecture for six commonly used DSP algorithms; Gain, Mix, Gain and Mix,Complex Number Multiplication, Envelope Detection and Cascaded IIR Filter. Toensure optimal performance, the instructions should be scheduled with minimalpipeline stalls. This requires execution time to be measured with fine time granularity.First, a technique of accurately measuring the execution time using thecycle counter of the processor’s Performance Management Unit(PMU) along withsynchronization barriers is developed. It was found that the execution time measuredby using the operating system calls have high variations and very low timegranularity, whereas the cycle counter method was accurate and produced reliableresults. The cost associated with the cycle counter method is 75 clock cycles. Usingthis technique, the contribution by each SIMD instruction towards the executiontime is measured and is used to schedule the instructions. This thesis also presentsa guideline on how to schedule instructions which have data dependencies usingthe cycle counter timing execution time measurement technique, to ensure that thepipeline stalls are minimized. The algorithms are also modified, if needed, to favorvectorization and are implemented using ARM architecture specific SIMD instructions.These implementations are then compared to that which are automaticallyproduced by the compiler’s auto-vectorization feature. The execution times of theSIMD implementations was much lower compared to that produced by the compilerand the speedup ranged from 2.47 to 5.11. Also, the performance increaseis significant when the instructions are scheduled in an optimal way. This thesisconcludes that the auto-vectorized code does poorly for complex algorithms andproduces code with a lot of data dependencies causing pipeline stalls, even with fulloptimizations enabled. Using the guidelines presented in this thesis for schedulingthe instructions, the performance of the DSP algorithms have significant improvementscompared to their auto-vectorized counterparts. / Digitala signalbehandlingsalgoritmer(DSP) implementeras ofta i realtidssystem. Inomfält som exempelvis digital musikteknik används dessa algoritmer, ofta i olika kombinationer,för att ge önskad funktionalitet. Implementationen av DSP-algoritmerär prestandakritisk eftersom systemen ofta har små tidsmarginaler. I det härexamensarbetet genomförs prestandaoptimering med Single Instruction MultipleData(SIMD)-vektorisering på en ARM A15-arkitektur för 6 vanliga DSP-algoritmer;volym, mix, volym och mix, multiplikation av komplexa tal, amplituddetektering,och seriekopplade IIR-filter. Maximal optimering av algoritmerna kräver ocksåatt antalet pipeline stalls i processorn minimeras. För att kunna observera dettakrävs att exekveringstiden kan mätas med hög tidsupplösning. I det här examensarbeteutvecklas först en teknik för att mäta exekveringstiden med hjälp aven klockcykelräknare i processorns Performance Management Unit(PMU) tillsammansmed synkroniseringsbarriärer. Tidsmätning med hjälp av operativsystemsfunktionervisade sig ha sämre noggrannhet och tidsupplösning än metoden medatt räkna klockcykler, som gav tillförlitliga resultat. Den extra exekveringstidenför klockcykelräkning uppmättes till 75 klockcykler. Med den här tekniken är detmöjligt att mäta hur mycket varje SIMD-instruktion bidrar till den totala exekveringstiden.Examensarbete presenterar också en metod att ordna instruktioner somhar databeroenden sinsemellan med hjälp av ovanstående tidsmätningsmetod, såatt antalet pipeline stalls minimeras. I de fall det behövdes, skrevs koden till algoritmernaom för att bättre kunna utnyttja ARM-arkitekturens specifika SIMDinstruktioner.Dessa jämfördes sedan med resultaten från kompilatorns automatgenereradevektoriseringkod. Exekveringstiden för SIMD-implementationerna varsignifikant kortare än för de kompilatorgenererade och visade på en förbättring påmellan 2,47 och 5,11 gånger, mätt i exekveringstid. Resultaten visade också på entydlig förbättring när instruktionerna exekveras i en optimal ordning. Resultatenvisar att automatgenererad vektorisering presterar sämre för komplexa algoritmeroch producerar maskinkod med signifikanta databeroenden som orsakar pipelinestalls, även med optimeringsflaggor påslagna. Med hjälp av metoder presenteradei det här examensarbete kan prestandan i DSP-algoritmer förbättras betydligt ijämförelse med automatgenererad vektorisering.

Information is often stored and transmitted through electrical signals. This information may need refinement, which may be done by processing and altering the electrical signals, in which it is transmitted. When refining a signal, a frequency selective filter is often used. It can be implemented through digital signal processing (DSP). DSP is a concept where signals are refined using a digital compute system. Digital systems are designed to replace their analog counterpart, mitigating their flaws in scalability, complexity and cost. A DSP system is typically implemented using software on a small computer, while analog systems are implemented through various electronic components. The objective of this project is to design a DSP system that filters analog input data using automatically synthesised filters from user-defined input specifications. The DSP system is implemented using a microcontroller. The system designed the filters and found the filter coefficients. It then uses analog to digital converter (ADC) to sample an input signal and applies the filter. Lastly, it uses the digital to analog converter (DAC) to reconstruct a filtered, analog result. A user interface is not designed for the system, and only a limited number of filters are implemented. However, the system is successful in designing filters and finding their coefficients.

No description available.

This study deals with reading problems faced by the advanced level students in the Institute of International Relations (I.I.R.) in Hanoi. It seeks to identify ways in which the teachers there can help their students to read authentic texts in English with a high level of comprehension. The study begins with a description of the training of the young diplomats and researchers. It considers the problems faced by the teachers and students, and looks into the role of English in general and English reading comprehension in particular in the I.I.R. Bearing in mind the objectives of the training, the study discusses the goals for teaching reading comprehension at an advanced level and lays emphasis on the importance of using appropriate techniques for teaching reading skills at this level. The writer of the study also looks at the relevant issues in theories of reading comprehension which are discussed in current literature. These theoretical issues are then related to the reality of teaching in the I.I.R. Finally, to illustrate all the techniques and skills for teaching reading comprehension which have been dealt with earlier in the study, the writer presents a sample reading lesson. It is his hope that the presentation, and indeed the whole study, will be of value to his colleagues at the I.I.R., and to others who teach reading in similar situations.

<p>To effectively demonstrate the strength of using digital signal processing when producing sound effects, a sound effects demo is used at the lectures of the course TSRT78, Digital signal processing, which is given at the university in Linköping.</p><p>The amount of effects, that in an instructive way can be used for an educational purpose, are many and the existing version of the sound effects demo is somewhat limited in its range of effects.</p><p>This reports main focus lies in the presentation of what kind of effects which can be interesting in this kind of demo. All of the effects are presented with their background theory and examples on how they can be implemented in software, mainly with the focus on MATLABTM. Investigations on how well the effects can be run in realtime, in the toolbox SimulinkTM, has been made.</p><p>In the report there is also a presentation of a new version of the sound effect demo that has been produced with user friendlieness and further updates in mind. In the new demo all of the effects are implemented, according to their presentations. The report finishes with suggestions for further work on the sound effects demo.</p>

To effectively demonstrate the strength of using digital signal processing when producing sound effects, a sound effects demo is used at the lectures of the course TSRT78, Digital signal processing, which is given at the university in Linköping. The amount of effects, that in an instructive way can be used for an educational purpose, are many and the existing version of the sound effects demo is somewhat limited in its range of effects. This reports main focus lies in the presentation of what kind of effects which can be interesting in this kind of demo. All of the effects are presented with their background theory and examples on how they can be implemented in software, mainly with the focus on MATLABTM. Investigations on how well the effects can be run in realtime, in the toolbox SimulinkTM, has been made. In the report there is also a presentation of a new version of the sound effect demo that has been produced with user friendlieness and further updates in mind. In the new demo all of the effects are implemented, according to their presentations. The report finishes with suggestions for further work on the sound effects demo.

The recent popularity and convenience of Wireless communication and the need for integration demands the development of Software Defined Radio (SDR). First defined by Mitoal, the SDR processed the entire bandwidth using a high resolution and high speed ADC and remaining operations were done in DSP. The current trend in SDRs is to design highly reconfigurable analog front ends which can handle narrow-band and wideband standards, one at a time. Charge sampling has been widely used in these architectures due to the built in antialiasing capabilities, jitter robustness at high signal frequencies and flexibility in filter design. This work proposed a 1GHz wideband front end aimed at SDR applications using Transform Domain (TD) sampling techniques. Frequency Domain (FD) sampling, a special case of TD sampling, efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate and is a potential candidate for SDR. The proposed front end converts the RF signal into current and then it is downconverted using passive mixers. The front end has five parallel paths, each acting on a part of the spectrum effectively parallelizing the front end and relaxing the requirements. An overlap introduced between successive integration windows for jitter robustness was exploited to create a novel sinc2 downsample by two filter topology. This topology was compared to a conventional topology and found to be equivalent and area efficient by about 44%. The proposed topology was used as a baseband filter for all paths in the front end. The chip was sent for fabrication in 45nm technology. The active area of the chip was 6:6mm2. The testing and measurement of the chip still remains to be done.

Conventional methods of CFAR detection always use windowing, in the sense that some number of cells are investigated and the target present/absent decision is made according to the composition of the cells in that window. The most commonly used versions of CFAR detection algorithms are cell averaging CFAR, smallest of cell averaging CFAR, greatest of cell averaging CFAR and order-statistics CFAR. These methods all use windowing to set the decision threshold. In this thesis, rather than using windowed CFAR algorithms, a new method of estimating the background threshold is presented, analyzed and simulated. This new method is called the Switching IIR CFAR algorithm and uses two IIR filters to accurately estimate the background threshold. Then, using a comparison procedure, one of the filters is selected as the current threshold estimate and used. The results are seen to be satisfactory and comparable to conventional CFAR methods. The basic advantages of using the SIIR CFAR method are computational simplicity, small memory requirement and acceptable performance under clutter edges and multiple targets.

In this thesis, we considered the deconvolution problem when the channel is known a priori. LSE and MSE optimum solutions are investigated with deterministic and statistical approaches. We derived closed form LSE expressions and investigated the factors that affect the FIR inverse filters. It turns out that, minimum LSE can be obtained when the system zeros are distributed homogeneously on the z-plane. We proposed partition-based FIR-IIR inverse filters. The selection of FIR and IIR parts is based on partitioning the channel zeros into two regions and using the specified channel zeros to design the best delay FIR and all pole IIR inverse filters. Three methods for partitioning are presented, namely unit circle-based, ring-based and optimum-partitioning. It turns out that ring-based and optimum-partitioning FIR-IIR inverse filter performs better than the best delay FIR inverse filter for the same complexity by about 4-5 dB. For noisy observations, it is shown that, noise should also be considered in the delay selection and partitioning. We extended our results for the design of MSE optimum statistical inverse filters. It is shown that best delay FIR-IIR inverse filters are less sensitive to the estimation errors compared to the IIR Wiener filters and they perform better than the FIR Wiener filters. Furthermore, they are always causal and stable making them suitable for real-time implementations. When the statistical and deterministic filters are compared, it is shown that for low SNR statistical filters perform better by about 1-2 dB, while deterministic filters perform better by about 0.5-1 dB for high SNR