Στα πλαίσια αυτής της εργασίας παρουσιάζεται ένα ενσωματωμένο σύστημα χαμηλού κόστους το οποίο καταγράφει, αποθηκεύει και επεξεργάζεται αναπνευστικό σήμα που έχει ληφθεί κατά τη διάρκεια ανθρώπινου ύπνου. Στα κεφάλαια που ακολουθούν αναλύεται η δομή ,οι επιμέρους συνιστώσες του συστήματος καθώς και μέθοδοι επεξεργασίας του σήματος. Αρχικά λοιπόν ορίζεται το ιατρικό και θεωρητικό υπόβαθρο πάνω στο οποίο στηρίζονται οι ισχυρισμοί και μέθοδοι που ακολουθούνται. Εν συνεχεία, γίνεται εισαγωγή στους στοιχειώδεις ορισμούς όπως αυτοί του μικροελεγκτή και ενσωματωμένου συστήματος και γίνεται μια πρώτη αναφορά στο μικροελεγκτή ADuC 7026 της Analog Devices που χρησιμοποιήσαμε και στα περιφερειακά αυτού. Επίσης γίνεται και ανάλυση των στοιχειωδών χαρακτηριστικών του περιβάλλοντος μVision της Keil που μας επιτρέπουν να κάνουμε προσομοιώσεις με μηδενικό υλικό στη διάθεσή μας. Στο επόμενο κεφάλαιο γίνεται αναλυτική επεξήγηση του μικροελεγκτή μας και δίνονται επιπλέον ενδεικτικά παραδείγματα με τα οποία γίνεται κατανοητές βασικές δυνατότητες που προσφέρει αυτός και στις οποίες θα στηριχθούμε για να δομήσουμε το δικό μας πρόγραμμα. Σημειώνουμε εδώ πως ο προγραμματισμός του μικροελεγκτή και των περιφερειακών του έγινε σε γλώσσα προγραμματισμού C. Στο τέταρτο κεφάλαιο επεξηγούμε τον αλγόριθμο που χρησιμοποιήσαμε για την επεξεργασία του σήματος και τους λόγους επιλογής του. Έπειτα παραθέτουμε αναλυτικά τον κώδικα της εφαρμογής μας και τέλος καταλήγουμε σε αποτελέσματα και συμπεράσματα. / Within this thesis, we present a low cost embedded system that records, stores and processes the respiratory signal of snores obtained during human sleep. In the following chapters we analyze the structure, each component of the system and the methods being implemented. Initially we define the medical and theoretical background on which we are based to build in our program and apply our methods. Moreover, we give the basic definitions such as the microcontroller's and the embedded system’s, and we make the first presentation of The next the microcontroller ADuC 7026 of Analog Devices and its peripherals that will be used for implementation. We also present the μVision Keil environment which enables us to emulate the microcontroller having at our disposal zero hardware. The next section gives a detailed explanation of this microcontroller and some basic examples of its programming possibilities are presented that will help us with the application. The programming of the microcontroller and its peripherals was done in C programming language. In the fourth chapter we explain the algorithm that will be used for the signal processing and the reasons for its selection. Afterwards the programming of the microcontroller is given and explained in detail and finally we conclude with the results.

In October 2021, 137 countries and jurisdictions agreed on a common approach towards a global minimum tax of 15% on the profits of large multinational companies that is referred to as the Pillar Two Model Rules, ‘Anti Global Base Erosion’, or ‘GloBE’ Rules. This political agreement implies that member countries who wish to implement such a tax regime have to streamline its design by modelling it after the so called Global Anti-Base Erosion Proposal (‘GloBE’) that the IF has developed as ‘Pillar 2’ of its work program on tax challenges arising from the digitalization of the economy. On 17 June 2015, the European Commission presented an Action Plan for a fairer and more efficient corporate tax system in the European Union (EU). The powerful document re-defines the future course of corporate taxation in the EU. The GloBE Model Rules are an opportunity – an impulse – for the European Union to begin coordinating tax rates in corporate income tax among its Member States and to proceed further, in the near future, in the direction of harmonizing those rates. On December 22, 2021, the European Union (EU) announced the Proposal for a Directive to ensure a global minimum level of taxes for multinational groups. It follows the Pillar Two implementation planoutlined in the Inclusive Framework (IF) statement released on October 8, 2021, and the model rules published on December 20, 2021.5In this thesis the authors focus on whether the Global Anti-Base Erosion (‘GloBE’) rules, specifically Income Inclusion Rule, as set out in an Organisation for Economic Co-Operation and Development (‘OECD’) Blueprint of October 2020, comply with the EU fundamental freedoms. This compatibility is tested based on two differentscenario’s. In the first scenario the assumption is taken that the GloBErules will be implemented directly by the Members States (Assumption A). It will be addressed by the rule of reason doctrine by analysing which freedoms are getting affected then making a restriction test, then justification test and finally the proportionality test. In the second assumption is that the GloBE-rules will be implemented indirectly through an EU Directive (Assumption B). This analysis will show that, even though the GloBE-rules conflict with the freedom of establishment, they could still be implemented effectively because of the considerable discretion granted to the Union legislature by the Court of Justice of the European Union (CJEU).7 The directive at discussion in the thesis is the Minimum tax directive 2022/2523.

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No / Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, are now most often realized by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs. In this paper, distributed arithmetic (DA) realization of FIR filter as serial and parallel are discussed in terms of hardware cost and resource utilization.

Orientador: Prof. Dr. Luiz Alberto Luz de Almeida / Coorientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, Santo André, 2018. / O trabalho apresenta uma extensao da limitacao estatica Loop Proximity (..2..) do modelo de histerese para incorporar a componente reversivel de magnetizacao dependente de taxa para modelar nucleos de ferrite de energia e, possivelmente, materiais ferromagneticos baseados em ferro e niquel para aplicacoes de baixa frequencia. O modelo proposto e baseado em a combinacao do modelo estatico (..2..) com um filtro discreto dinamico linear de uma resposta de impulso infinita. Dois casos em que a histerese depende da frequencia de excitacao apresentada usando dados sinteticos para validar a capacidade do modelo para representar o comportamento de nucleos fisicos reais. A tecnica de otimizacao por enxames de particulas e empregada como um metodo para estimacao de parametros no resultado modelo estatico-dinamico nao linear. Os resultados da simulacao sao apresentados indicando que trouxemos a comunidade eletronica de potencia um modelo de nucleo promissor e alternativo para componentes magneticos usado em fontes de energia renovaveis. / We present an extension of the static Limiting Loop Proximity ..2.. hysteresis model to incorporate reversible magnetization and rate-dependency to model power ferrite cores and, possibly, ferromagnetic materials based on iron and nickel for low-frequency applications. The proposed model is based on the combination of the ..2.. static model with a dynamical discrete linear filter of an infinite impulse response. Two cases where the hysteresis depends on the excitation frequency are presented using synthetic data to validate de capacity of the model to behave as real physical cores. The particle swarm optimization is employed as a method for parameter estimation in the resulting nonlinear static-dynamic model. Simulation results are presented indicating that we brought to the power electronic community apromising and alternative core model for magnetic components used in renewable power sources.

This diploma thesis is engaged in implementations of algorithms for signal filtering in the field programmable gate array utilising the C and ImpulseC programming language. It is focused on one-dimensional FIR and IIR filters and also two-dimensional such as convolution and Sobel's operator. Moreover, evaluations of these filter algorithms are included.

Increasing sampling rates and sampling accuracies of analog-to-digital converters (ADCs) are growing the importance of digital data acquisition and signal processing for applications requiring high bandwidth. In this context, this work is focused on researching and developing new techniques and a new system architecture for optimal throughput and minimal intrinsic dead time. The investigations of this work concentrate on event processing systems by pulse shaping on SuperSampleRate (SSR) ADC data streams. SSR ADC data streams are data streams which require processing of more than one sample per clock cycle by digital circuits. To implement data processing in this work only Field Programmable Gate Arrays (FPGAs) are used, as they provide the right approach for high throughput and minimum dead time with ability to adapt to high- application-specific circuits afterwards. As a result of this work a system architecture was developed which decouples the event acquisition and their processing inside the FPGA. This property is realized by a special FIFO structure in the FPGA. This concept achieves an intrinsic dead time of one ADC sample period and allows pre-processing of all channels by multiple instantiated processing cores and scheduling in hardware. By means of this new system architecture, two conventional scientific measuring instruments based on analog technology were improved by digital data acquisition and signal processing. These measuring instruments are a spectrometer for time-differential perturbed angular correlations (TDPAC) and a digital spectrometer and data acquisition system at a nuclear microprobe for ion beam analysis and imaging. Both measuring instruments detect elementary particles or radiation emitted by the measuring sample by detectors as events. The time curves of several analog detector output signals (channels) are now recorded by ADCs and forwarded without loss as SSR data streams to one FPGA. The hardware used here are FPGA digitizers which isolate the data acquisition and subsequent pre-processing by FPGAs into modules. The improvement of the measuring efficiency of the two digital measuring instruments was achieved by minimizing the dead time, increasing the throughput, and by matching their time and energy resolutions with the conventional measuring instruments. Specifically to enable better time and energy resolutions combined with maximum throughput, this work has developed and implemented parallel processing SSR FIR and SSR IIR filters for pulse shaping as processing cores in the FPGAs which can handle multiple samples per clock cycle. To match the time resolution performance of conventional Constant Fraction Discriminators (CFDs) these filter implementations realize a digital Constant Fraction Trigger (CFT) with fractional delays (below one sampling period). In this work the energy resolution was optimized by implementing a transfer function adjustable SSR IIR filter. Thus the filter provides maximum flexibility for pulse shaping of different detector types. By implementing the computationally intensive pre-processing in FPGAs, the measuring instruments could be equipped with only one underutilized PC, which can now implement new functionalities. These functionalities include a runtime-optimized coincidence measurement of stretched cascades (like for 180mHf) for the TDPAC spectrometer and a digital pileup rejection for the data acquisition system for ion beam analysis. / Die digitale Messwerterfassung und -verarbeitung erhält unter anderem durch steigende Abtastraten und Abtastgenauigkeiten von Analog-Digital-Wandlern (ADCs) wachsende Bedeutung für Anwendungen, welche eine hohe Bandbreite voraussetzen. In diesem Rahmen widmet sich diese Arbeit der Erforschung und Entwicklung neuer Techniken und einer neuen Systemarchitektur, mit denen eine Datenaufnahme und anschließende Signalverarbeitung, bei optimalem Durchsatz und minimaler intrinsische Totzeit umgesetzt werden kann. Die Untersuchungen fokussieren sich dabei auf Systeme zur Ereignisverarbeitung durch Impulsformung (pulse shaping) auf SuperSampleRate(SSR)-ADC-Datenströmen. SSR-ADC-Datenströme sind dabei ADC-Datenströme, welche eine Verarbeitung durch digitale Schaltungen benötigen, bei denen mehr als ein Sample pro Taktzyklus behandelt werden muss, um Datenverlust zu verhindern. Zur Implementierung der Datenverarbeitung kommen dazu ausschließlich Field Programmable Gate Arrays (FPGAs) zum Einsatz, da diese den passenden Ansatz für digitale Schaltungen mit hohen Durchsatz und minimaler Totzeit mit gleichzeitiger nachträglicher Anpassbarkeit für hoch anwendungsspezifische Schaltungen bieten. Als Ergebnis wurde in dieser Arbeit eine Systemarchitektur entwickelt, welche die Ereigniserfassung und deren Verarbeitung im FPGA voneinander entkoppelt. Dies wird durch eine im FPGA realisierte FIFO-Struktur ermöglicht. Durch dieses Konzept wird eine intrinsische Totzeit der Systeme in der Größenordnung der ADC-Abtastperiodenlänge erreicht und eine Vorverarbeitung aller Kanäle durch mehrfache instanziierte Verarbeitungskerne und Scheduling in Hardware ermöglicht. Mittels dieser neuen Systemarchitektur werden zwei auf analogtechnisch basierende konventionelle wissenschaftliche Messinstrumente, durch digitale Messwerterfassung und Signalverarbeitung, verbessert. Bei diesen Messinstrumenten handelt es sich um ein Spektrometer zur zeitaufgelösten gestörten Winkelkorrelation (engl. Time Differential Perturbed Angular Correlation (kurz TDPAC-Spektrometer)) und ein Datenerfassungssystem zur ortsaufgelösten elementspezifischen Ionenstrahlanalyse und Ionenstrahlmikroskopie, welche im Wesentlichen von der Messprobe emittierte und durch Detektoren erfasste Elementarteilchen oder Strahlung als Ereignisse verarbeiten. Die Verläufe der analogen Detektorausgangssignale werden dabei mittels ADCs erfasst und verlustfrei als SSR-Datenströme an einen FPGA weitergeleitet. Dabei werden mehrere ADC-Datenströme (dann Kanäle genannt) von einem FPGA verarbeitet. Als Hardware kommen hier FPGA-Digitizer zum Einsatz. Diese Module isolieren die digitale Messwerterfassung durch ADCs und eine anschließende Vorverarbeitung von FPGAs, deren digitale Schaltung individuell implementiert werden kann, in eine Hardware. Eine Verbesserung der Messeffizienz der beiden digitalisierten Messinstrumente konnte durch die Minimierung der Totzeit, die Erhöhung des Durchsatzes aber auch durch die Anknüpfung ihrer Zeit- und Energieauflösung der detektierten Ereignisse erreicht werden. Speziell zur Ermöglichung besserer Zeit- und Energieauflösungen von Detektorereignissen mit maximalem Durchsatz wurden in dieser Arbeit SSR-FIR- und SSR-IIR-Filter zur Impulsformung als Verarbeitungskerne in den verwendeten FPGAs implementiert, welche pro Taktzyklus mehrere Samples verarbeiten können. Diese Filterimplementierungen setzen zur Optimierung der Zeitauflösung im Subsample-Bereich mit den Constant Fraction Trigger (CFT) an der Leistungsfähigkeit konventioneller Constant Fraction Discriminator (CFDs) an und ermöglichen ebenso Fractional Delays (Zeitverzögerungen unter einer Abtastperiode). Die Energieauflösung wurde in dieser Arbeit dadurch optimiert, dass der entwickelte SSR-IIR-Filter in seiner Übertragungsfunktion anpassbar ist und so maximale Flexibilität zur Impulsformung unterschiedlicher Detektortypen bietet. Durch die Umsetzung der rechenintensiven Vorverarbeitung in FPGAs konnten die Messinstrumente mit lediglich einem Mess-PC ausgestattet werden, welcher nun neue Funktionalitäten umsetzen kann. Zu diesen Funktionalitäten gehört eine laufzeitoptimierte Koinzidenzmessung gestreckter Kaskaden (Kaskade mit mehr als einem Start-Ereignis) für das TDPAC-Spektrometer und eine digitale Pileup-Verwerfung für das Datenerfassungssystem zur Ionenstrahlanalyse.

The thesis aims to implement different digital filters such as finite impulse response (FIR), infinite impulse response (IIR) and cascade integrator comb (CIC) on the field-programmable gate array (FPGA) development board using hardware description language (VHDL). To this purpose, Intel’s systems integration tool Platform designer is used to convert the implementation to an IP core. The implemented FIR and IIR filters include different filter types such as lowpass, highpass, bandpass and bandstop. All the filters have a pipeline architecture as well as adjustable parameters such as filter order, frequency specifications and resolution. The coefficients of the filters are calculated according to the user's specifications. The calculated coefficients are verified using simulation. Furthermore the IP has been validated on hardware by the FPGA board MAX DE-10 lite. The IP is also analyzed regarding timing and power consumtion with good results. FIR filters of different types have been implemented and tested up to 501 taps with a coefficient width of 24 bits, which covered just below 50% of the available logic gates on the MAX 10-DE lite board with 50000 gates in total. The FIR filters have an option to be used with a Kaiser window with a maximum tap level of 51. Different IIR filters have also been implemented and tested on the hardware. However, the results have shown that the IIR filters do not perform so well, especially those of order higher than 6. One of the main reasons for this is the overflow caused by instability of the IIR.

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