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The advances in integrated circuit fabrication technology, coupled with the emergence of independent silicon foundries, has made it commercially viable to fabricate low volume Application Specific Integrated Circuits (ASICs). However, given the complexity of such systems it is becoming uneconomical to <I>design</I> them using conventional computer aided design (CAD) techniques. One approach to solving the so called "design crisis" has been to develop design tools which can synthesise an entire silicon architecture from an algorithmic description of its functionality. Such systems are referred to as high level synthesis systems. Interconnect is a major cost in VLSI devices and its effects are difficult to estimate in high level synthesis. As such, many existing high level synthesis systems use quite weak interconnect estimation heuristics which lead to inefficient layout when the synthesised structure is mapped into the physical domain. The presented approach defines a partitioned target architecture and bit-sliced layout style which may virtually eliminate the need for global wiring and hence obviate the problem of interconnect estimation. The structural cost of the synthesised architecture is therefore more closely associated with the real physical cost when realised on chip. This target architecture is used as the basis for the CASS high level synthesis system which performs algorithmic behavioural synthesis for digital signal processing (DSP) applications. A detailed discussion of the algorithms in the CASS tools is given and presented area estimates show that significant area savings are attainable by using the defined architecture and layout style. The development of CASS inspired a successor system which performs high level synthesis in one global optimisation. COBRA performs synthesis by optimising a mapping of variable lifetimes in a three dimensional "datapath space" using the method of simulated annealing.

The link between sustainability and the planning process has been legislated and polices applied but the practical rhetoric and implementation thereof remains problematic (Oranje & Van Huyssteen, 2004 and Owens, 1994). An integral part of that link is the ability of the planning process to provide for public involvement. However within institutionalized planning processes the dominance of “experts” (scientific based) in the process allows for an exclusionary debate with regard to local issues (Eden, 1996). This research explored the ability of the local legislated integrated development planning (IDP) process as a tool through which the implementation of sustainability could be fostered. It specifically explored the discourse of knowledge (scientific, counter scientific and non scientific) as a construct in implementing deliberative public participation for sustainability. The qualitative approach utilized in this study employed multiple research methodologies through the utilization of the Lesedi Local Municipality (LLM) IDP process as a case study. This research report shows that while the IDP is a technical process paying little attention to other knowledge’s, it does have some potential as a framework that can aid in the implementation of sustainable participation through its ability to empower communities and foster community led development through ownership of this local process.

A project report submitted to the Faculty of Engineering, University of the Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the degree of Master of Science in Engineering. / This project report examines the performance of three VLSI U-interface implementations satisfying the requirements of Basic Access on an ISDN. The systems evaluated are the Intel 89120,Siemens PEB2090 and STC DSP144, operating on 2BIQ, MMS4J and SU32 line codes respectively. Before evaluating the three abovementioned systems, a review of the underlying principles of U-interface technology is presented. Included in the review are aspects of transmission line theory, line coding, echo-cancellation, decision feedback equalisation, and pulse density modulation. The functional specifications of the three systems are then presented followed by a practical evaluation of each system. As an aid to testing the transmission systems, an evaluation board has been designed and built. The latter provides the necessary functionality to correctly activate each system, as well as the appropriate interfacing requirements for the error-rate tester. The U-interface transmission systems are evaluated on a number of test-loops, comprising sections of cable varying in length and gauge. Additionally, impairments are injected into data-carrying cables, in order to test the performance of each system in the presence of noise. The results of each test are recorded and analysed. Finally, a recommendation is made in favour of the 2BIQ U-interface. It is shown to offer superior transmission performance, at the expense of a slightly higher transmit-power level. / Andrew Chakane 2018

Digitized by Kansas Correctional Industries

隨著工藝尺寸的縮小，集成電路的時序行為變得越來越難以預測，某原因在於各種偏差效應，比如製造偏差、供電電壓波動以及溫度變化。對於傳統的“確保正確“的設計方式，我們需要留出很大的餘量，這就減少了工藝進步帶來的好處。時序監測C Timing Speculation) 因為具有錯誤檢測和更正機制而成為一種很有前景的解決辦法。採用這種方式，電路可以工作在有不太頻繁時序錯誤的情況下。而對於這種時序監視的設計方式，現有的優化方法大多主要是在電路結構確定之後的一些小的改動。因為這些方法無法對電路結構進行改變，所以它們的效果很有限。因此，我們在這篇論文里提出了在電路綜合(synthesis)過程中的一些優化方法，這些方法是能夠改變電路結構的。我們提出的優化方法主要集中在優化電路的硬件開銷和電路性能的方面。我們提出的方法主要包括兩個設計階段。 / 第一個階段是在邏輯綜合(Logic synthesis) 的時候.在邏輯綜合的時候，我們有很大的自由度去根據時序監測的特性來改變電路的結構。如果結合了特殊的實現方法，電路出現時序錯誤的頻率就會得到降低，從而提高了電路的性能。 / 第二個階段是在邏輯綜合之後的后綜合(Post-synthesis) 階段。為了減少時序監測的硬件上的開銷，我們提出了基於retiming 手法的再綜合(resynthesis) 方法.這種方法可以減少可疑寄存器(suspicious FF) 的數量從而降低硬件開銷。另外這種辦法也可以提高電路的吞吐量(throughput) 。為了進一步對電路進行優化，我們挨著又提出了基於rewiring 手法的電路吞吐量優化方法。此外，利用這種方法我們還可以消除部份電路里的短通路(short path) 從而進一步減少電路的硬件開銷。在這個階段，我們仍然具有改變電路結構的靈活性，因此我們的方法具有很好的效果。 / With technology scaling, the timing behavior of integrated circuits (ICs) becomes more unpredictable due to various variation effects, such as manufacturing variability, voltage fluctuations and temperature changes. A large design guard band is therefore reserved to ensure “always correct“ operation for traditional designs, disminishing the benefits of technology scaling. Timing speculation with error detection and correction mechanisms is a promising solution to tackle the above problem. With this technique, circuit can work under infrequent timing errors. The existing optimization techniques for timing speculated circuits are mainly based on some small modifications after the circuit structure is determined. Without the ability to change circuit structure, the efficiency is limited. Therefore, in this thesis we propose optimization techniques during the process of synthesis so that the flexibility is provided to make circuit structural change. Our optimization fo¬cuses on hardware cost and circuit performance and the proposed techniques are included in two design steps. / First step is logic synthesis. During the process of logic synthesis, there is large flexibility to change the circuit structure by considering the features of timing speculation. With intentional strategy the timing error probability can be reduced so as to improve the circuit throughput. / Second step is post-synthesis techniques after logic synthesis. To reduce the hardware cost for timing speculation, we propose a re-synthesis method based on the idea of retiming to reduce the number of suspicious FFs where timing errors mainly happen. This technique can also help to improve the circuit throughput if carefully implemented. To further improve the throughput, we also propose to use rewiring technique which is also called redundancy addition and removal (RAR) to optimize circuit for throughput. Furthermore, this technique can also be used to break down short paths so as to save the hardware cost. During this step, flexibility is also provided to make circuit structural change so that the efficiency is guaranteed. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Liu, Yuxi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 70-76). / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Timing Speculation --- p.1 / Chapter 1.1.1 --- Circuit Timing Problem --- p.1 / Chapter 1.1.2 --- Possible Solution --- p.3 / Chapter 1.1.3 --- Timing Speculation is Promising --- p.4 / Chapter 1.1.4 --- Razor Flip-flop --- p.5 / Chapter 1.2 --- Problems for Timing Speculation --- p.6 / Chapter 1.2.1 --- Hardware Cost of Timing Speculation --- p.7 / Chapter 1.2.2 --- Performance of Timing Speculation --- p.8 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 1.4 --- Thesis Contributions --- p.11 / Chapter 2 --- Logic Synthesis for Timing Speculation --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Preliminaries --- p.14 / Chapter 2.2.1 --- Timing Speculation --- p.14 / Chapter 2.2.2 --- AIG-Based Logic Synthesis --- p.15 / Chapter 2.3 --- Logic Synthesis for Timing Speculation --- p.16 / Chapter 2.3.1 --- Proposed Optimization Metric --- p.17 / Chapter 2.3.2 --- Proposed Logic Synthesis Solution --- p.19 / Chapter 2.4 --- Experimental Results --- p.24 / Chapter 2.4.1 --- Experimental Setup --- p.24 / Chapter 2.4.2 --- Results and Discussion --- p.25 / Chapter 2.5 --- Conclusion --- p.30 / Chapter 3 --- Post-Synthesis Optimization for Timing Speculation --- p.31 / Chapter 3.1 --- Optimization for Timing Speculation by Retiming --- p.32 / Chapter 3.1.1 --- Introduction --- p.32 / Chapter 3.1.2 --- Preliminaries and Motivation --- p.33 / Chapter 3.1.3 --- Reducing Suspicious FFs by Retiming --- p.35 / Chapter 3.1.4 --- Reducing Timing Error Probability by Retiming --- p.41 / Chapter 3.1.5 --- Padding Short Paths --- p.43 / Chapter 3.2 --- Optimization for Timing Speculation by Rewiring --- p.47 / Chapter 3.2.1 --- Introduction --- p.47 / Chapter 3.2.2 --- Preliminaries --- p.48 / Chapter 3.2.3 --- Timing Optimization by Rewiring --- p.52 / Chapter 3.2.4 --- Reduce Hardware Cost by Rewiring --- p.60 / Chapter 3.3 --- Experimental Results --- p.62 / Chapter 3.4 --- Conclusion --- p.66 / Chapter 4 --- Conclusion --- p.68 / Bibliography --- p.76

隨著半導體工藝技術的不斷進步 (technology scaling) ，更多的設計資源不得不用於確保集成電路的時序正確性。這種“面向最壞情況(worstcase-oriented) 的芯片設計方法導致了悲觀保守的芯片設計方案，增加了性能及功耗開銷，減少了工藝進步帶來的效益。 / “優於最壞情況(better-than-worst-case) 的芯片設計方法允許犧牲一定的芯片可靠性 (reliability) 來提高性能以及降低功耗，從而提高計算的能量效率 (energy efficiency) 。“優於最壞情況設計方法的核心思想在於放松對芯片可靠性的硬性需求。既然時序錯誤 (timing error) 在關鍵路徑中的發生頻率並不高，我們可以允許錯誤發生，從而節約用於防止錯誤發生所需要的高額開銷。而當錯誤發生時，再利用錯誤檢測和更正方法(error detection and correction) 來消除錯誤造成的影響。這種無須保證計算過程永遠正確無誤的方法通常被稱作“ 時序推測 (timing speculation) 。然而，不幸的是，由於傳統的“面向最壞情況的設計方法往往導致芯片中存在所謂的“關鍵路徑壁壘(wall of critical paths) ，時序推測技術的有效性在一定程度上受限。 / 為了解決上述問題，我們首先研究了時序推測技術的前提與前景，也就是研究了如何估計時序推測技術能夠帶來的最小和最大效益。此外，我們也研究了時序推測芯片 (timing-speculative circuit) 中的若幹設計優化問題。首先，由於引入時序推測技術能夠提高多電壓 (multi-supply voltage)技術的靈活性，我們闡述了時序推測芯片中的多電壓設計問題，並創造性地提出了一種基於動態規劃 (dynamic programming) 的算法來解決這個問題。此外，我們提出了時序推測芯片中的時鐘差異規劃 (clock skew scheduling) 問題。在考慮了時序錯誤率 (timing error rate) 等因素的影響後，我們設計了新穎有效的方法來解決該問題。最後，鑒於工藝差異(process variation) 和老化效應 (wearout effect) 對芯片時序的影響，而且這種影響很難在設計階段被消除，我們提出了一種實時的時序差異調整(clock skew tuning) 架構。利用精心設計的硬件結構，我們可以實時地收集時序錯誤的信息，相應地調整時鐘差異，從而極大地減弱了時序不確定性對芯片性能的影響。 / As circuit non-idealities inevitably worsen with technology scaling, more design resource has to be incorporated to ensure integrated circuit (IC) timing correctness. Such worst-case-oriented design methodology results in pessimistic designs with considerable power and performance overheads, lessening the benefits provided by technology scaling. / Better-than-worst-case (BTWC) design methodology that allows reliability to be traded off against power and performance was proposed to dramatically improve the computation energy-efficiency. The basic idea behind BTWC design methodology is that, since circuit non-idealities mainly manifest themselves as infrequent timing errors on critical paths of the circuit, we can over-clock operating frequency and/or over-scale supply voltage of the chip to a critical point, where timing errors occur, and achieve error-resilient computations by performing timing error detection and correction. This approach is generally referred to as timing speculation, with which it is not necessary to guarantee “always correct operations. Unfortunately, there is usually a “wall of critical paths in the final implementation of a circuit caused by conventional worst-case-oriented design methodology, suggesting that, given a fixed circuit design, the effectiveness of timing speculation is limited by a fixed threshold beyond which the circuit performance/energy efficiency will drop significantly. / To address the above problem, this thesis first proposes to study the premises and prospects of timing speculation by analyzing the minimum and maximum potential benefits that are achievable by timing speculation techniques. After answering the question posed by the conflict between conventional techniques and timing speculation, this thesis investigates multiple design and optimization problems in timing-speculative circuits. Firstly, as introducing timing speculation capability into circuits can naturally extend the flexibility of multi-supply voltage (MSV) designs to a new horizon, this thesis formulates the MSV design problem for timing-speculative circuits and develops a novel algorithm based on dynamic programming to solve it. Secondly, this thesis develops a general formulation of clock skew scheduling (CSS) problem for timing-speculative circuits, wherein timing error rate and its corresponding impact are explicitly considered, and proposes novel algorithms to tackle this problem. Finally, considering the impact of timing uncertainties caused by process variation and wearout effects, which is very difficult to be modeled and addressed at design stage, this thesis also develops a novel online clock skew tuning framework for timing-speculative circuits. By utilizing an elaborately-designed hardware architecture to collect timing error information and tune clock skews at runtime, variation effects can be effectively mitigated. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Ye, Rong. / Thesis (Ph.D.) Chinese University of Hong Kong, 2014. / Includes bibliographical references (leaves 131-142). / Abstracts also in Chinese.

Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g. 300-500mV) is a key technique to achieve high computing energy efficiency. It has enabled many new exciting applications in the field of Internet of Things (IoT) devices and energy-constrained applications such as medical implants, environment sensors, and micro-robots. Ultra-low-voltage (ULV) operation is also commonly used with the emerging architectures that are often non Von-Neumann style to empower energy-efficient cognitive computing. One the biggest challenge in realizing ULV design is the large circuit delay variability. To guarantee functionality in the worst-case process, voltage, and temperature (PVT) condition, the traditional safety margin approach requires operating at a slower clock frequency or higher supply voltage which significantly limits the achievable energy efficiency of the hardware. To fully claim the energy efficiency of ULV, the large circuit delay variation needs to be adaptively handled. However, the existing adaptive techniques that are optimized for nominal supply voltage operation and traditional Von-Neumann architectures become inefficient for ULV designs and emerging architectures. This thesis presents adaptive techniques based on timing error detection and correction (EDAC) that are more suitable for the energy-constrained ULV designs and the emerging architectures. The proposed techniques are demonstrated in three test chips: (1) R-Processor: A 0.4V resilient processor with a voltage-scalable and low-overhead in-situ EDAC technique. It achieves 38% energy efficiency improvement or 2.3X throughput improvement as compared to the traditional safety margin approach. (2) A 450mV timing-margin-free waveform sorter for brain computer interface (BCI) microsystem. It achieves 49.3% higher energy efficiency and 35.6% higher throughput than the traditional safety margin approach. (3) Ultra-low-power and robust power-management system which consists of a microprocessor employing ULV EDAC, 63-ratio integrated switched-capacitor DC-DC converter, and a fully-digital error based regulation controller. In this thesis, we also explore circuits for emerging techniques. The first is temperature sensors for dynamic-thermal-management (DTM). The modern high-performance microprocessors suffer from ever-increasing power densities which has led to reliability concerns and increased cooling costs from excessive heat. In order to monitor and manage the thermal behavior, DTM techniques embed multiple temperature sensors and use its information. The size, accuracy, and voltage-scalability of the sensor are critical for the performance of DTM. Therefore, we propose a temperature sensor that directly senses transistor threshold voltage and the test chip demonstrates 9X smaller area, 3X higher accuracy, and 200mV lower voltage scalability (down to 400mV) than the previous state-of-art. Another area of exploration is interconnect design for ultra-dynamic-voltage-scaling (UDVS) systems. UDVS has been proposed for applications that require both high performance and high energy efficiency. UDVS can provide peak performance with nominal supply voltage when work load is high. When work load is moderate or low, UDVS systems can switch to ULV operation for higher energy efficiency. One of the critical challenges for developing UDVS systems is the inflexibility in various circuit fabrics that are often optimized for a single supply voltage. One critical example is conventional repeater based long interconnects which suffers from non-optimal performance and energy efficiency in UDVS systems. Therefore, in this thesis, we propose a reconfigurable interconnect design based on regenerators and demonstrate near optimal performance and energy efficiency across the supply voltage of 0.3V and 1V.