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This dissertation is an account of experimental work conducted at the Microelectronics Research Laboratory of the Physics Department, Cambridge University. Structures have been studied, principally by electron microscopy, to assess the viability of a dual electron beam technique in the production of multiple layer structures. Silicon on insulator structures, where devices are made in individual islands of silicon on an insulating substrate, are of great use for many applications in microelectronics. One of these will be the use of multiple layers of devices in 'three dimensional' circuits. The dual electron beam technique is one way of producing silicon on insulator layers, and the experiments described here are performed on silicon films made by this method. For device applications, the silicon must be single crystal, and the technique uses seeding from a single crystal wafer. The film is grown by rapidly melting and recrystallizing a layer of polycrystalline silicon, and qualitative models of the regrowth process are presented. The results are also compared with quantitative models. Several investigations have been carried out to assess the suitability of the technique for producing stacked layers, where the recrystallization of upper layers must not adversely affect devices already formed in lower layers. The study has found that the dual electron beam technique is well suited to the formation of multiple silicon on insulator layers. The regrowth has been found to behave as predicted on a macroscopic scale, but shows features not previously observed when studied in detail. In particular, the existence of faceting of a submicron scale in the recrystallization front has been proven.

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A general schematic method is developed for modeling the fundamental parameters of vacuum integrated circuits (VIC's), a new class of microelectronics devices. A summary of the history of thermionic integrated circuits (TIC's) is presented, along with a discussion of the heater and its effect on device performance. The effects of the base metal on the emission properties of cathodes which are a mixture of the emission carbonates and negative photo-resist are also considered. The amplification factor is determined by using either a first or second order model depending on the desired degree of accuracy. The transconductance and anode resistance may be calculated as well by using the perveance model of cathode current. The voltage scaling factor used in the design of small voltage operating devices is applied to the analysis of planar devices. Electrostatic interactions between devices are important in the design of vacuum integrated circuits. The percent interaction function is used to quantify the effects of DC and small signal electrostatic interactions. The effect of work function differences on the DC biasing of circuits is also considered. The pseudo-radial electrostatic (PREF) lens is used to direct the electrons in a quasi-circular orbit from cathode to anode. The PREF lens is utilized in designing a series of planar devices including current source, triode (diode), enhancement-mode and depletion-mode type devices. The theory and experimentally determined characteristics of these devices are presented in detail.

There are several important semiconductor devices in which the transport of carriers is controlled by punch-through space-charge effects. Examples include the Bipolar Mode Static Induction Transistor (BSIT), ultrasmall Punch-through MOSFETs, and BARITT diodes for microwave applications. The development of punch-through space-charge type of devices is a technology motivated by the demanding high density among the IC chips. This dissertation discusses a device which operates in a punch-through condition with space-charge control of currents. It is a two terminal device, which could be fabricated with no deviation from today's technology. The device structure is simple, with two n⁺ or p⁺ regions formed in p⁻ or n⁻ substrate, respectively. Punch-through space-charge limited structures both n⁺p⁻n⁺ and p⁺n⁻p⁺, were simulated using a general one-dimensional semiconductor device performance simulation program GESIM1 for dynamic and static analysis. The results of simulation show that the potential barrier height decreases with increasing applied potential and with a reduction of the spacing L between the n⁺ diffusion in an n⁺p⁻n⁺ structure. The resistance increases as the spacing L is increased. A two-dimensional analytical model of carrier transport in the device was developed. This model accounts for surface effects as well as the space-charge limited flow. Also, a one-dimensional model that includes mobile carriers effects on the device operation. Structures of various configurations were fabricated and tested. Electrical evaluations of these structures provided large value resistors in a remarkably small area compare to traditional integrated resistors. The resistance was observed to increase with the spacing L and with the resistivity of the starting substrate. These punch-through space-charge limited loads should have applications as an alternative approach for integrated resistors in high-speed VLSI applications. They can provide very small area, large value resistors based on the space-charge limiting action of the device. The range of resistance value is large, and small dimensions lead to small capacitance and fast switching times.

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