- About
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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
Search results
Showing 111 to 120 of 7682 (0.044 seconds)| 111 |
A CUSTOM BIPOLAR MICROPROCESSOR SUPPORT INTEGRATED CIRCUITMiller, Ira, 1943- January 1986 (has links)
No description available.
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| 112 |
Analysis domain truncation of interconnections in multilayer packaging structuresGarg, Nitin Kumar, 1967- January 1989 (has links)
Interconnect lines, which connect components on a chip, can exhibit transmission line properties. Several factors like decrease in size of components, and decrease in spacing between interconnect lines, have contributed to the increase in importance of interconnect lines. A circuit-analysis approach that does not include the effect of these lines may be useless for highly dense chips. The presence of an active line does not require the analysis of all the other lines in a transmission-line system. In this thesis, a numerical experimental approach based on several industry-typical geometries is used to discuss analysis domain truncation of parallel conductors lying on a horizontal plane. It is found that "The maximum analysis domain between parallel conductors lying on a horizontal plane can be deduced from the analysis of the case of several similar, and parallel conductors of smallest possible width lying on a horizontal plane." UAC (University of Arizona Capacitance Calculator) is used as the TEM parameter extractor, while UACSL (University of Arizona Coupled Line Simulator With Linear Terminations) is used to calculate the voltages on the transmission lines.
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| 113 |
Efficient backtracking strategies in test generationYu, Tein-Yow, 1961- January 1989 (has links)
This thesis addresses the problem of backtracking strategies in test generation. First, a methodology which uses status of absolute dominators as a means for causing backtracking during the test generation process is presented. Then, different heuristics that force the test generation to execute the backtracking procedure are investigated. Experiments which generated test patterns for over 30,000 faults have been used to evaluate these heuristics. According to the experimental results, we recommend a new backtracking strategy that has the best performance among the six strategies explored in this thesis.
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| 114 |
Management of insect pests of farmed-stored maize in Kenya, with particular reference to Prostephanus truncatus (Horn)Giles, Peter H. January 1998 (has links)
No description available.
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| 115 |
An integrated Schottky-collector heterojunction bipolar transistorHall, S. January 1987 (has links)
No description available.
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| 116 |
Theoretical investigation of optical waveguide and fibre componentsFinegan, T. January 1987 (has links)
No description available.
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| 117 |
The development of a high-level synthesis system for concurrent VLSI systemsBergamaschi, Reinaldo Alvarenga January 1988 (has links)
No description available.
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| 118 |
Macrosimulation of LSI circuits for timing and waveform dataFyson, C. J. R. January 1986 (has links)
No description available.
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| 119 |
Wafer-scale integration of cellular architecturesBentley, L. January 1988 (has links)
No description available.
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| 120 |
On-chip testing of very large scale integrated circuitsVarma, P. January 1984 (has links)
No description available.
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