For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

This dissertation discusses the economic issues surrounding corruption at the firm-level in Nigeria with a specific focus on bribery. This involves an analysis of the paying and reporting of bribes by firm managers in Nigeria. The first chapter uses data from two business surveys to explain the determinants of the incidence of bribery and the magnitude of bribes, respectively. A two-stage analysis is conducted to test for the independence of the processes determining the incidence and the magnitude of bribery. The results show that the propensity to bribe is determined by required meetings with public officials while the size of bribe is driven by firm profitability indicators. The second chapter tests the reliability of methods used to ask individuals sensitive questions on different forms of business malpractice. Indirect methods are tested against the randomised response method. The indirect method protects the managers from stigmatisation by asking them about the behaviour of an agent representative of themselves; the randomised response method asks the interviewee to base their response on the result of a private coin-toss. The results show that the indirect method produces higher and more plausible estimates of wrongdoing than the andomised response method. The third chapter investigates why the randomised response method sometimes fails in eliciting honest responses from sensitive questions despite assuring the managers of anonymity. The roles of trust in the interviewer and the probability of detection are considered along with other potential explanations. Results indicate that lack of trust and the fear of detection are associated with underreporting of sensitive acts. The final chapter examines the relationship between bribery and ethnic networks. The ethnicities of the managers and their local political representatives are used to measure ethnic networks. Results show that co-ethnic firm managers are less likely to pay a bribe than non co-ethnics. Also, there is a positive association between ethno-linguistic fractionalisation and bribery which, in fractionalised areas, eradicates the negative effect of co-ethnicity on bribery.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123

Wong Sze Hon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 88-91). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Preliminaries --- p.1 / Chapter 1.2 --- Motivations --- p.1 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Organization of the Thesis --- p.4 / Chapter 2 --- VLSI Physical Design Automation --- p.5 / Chapter 2.1 --- Preliminaries --- p.5 / Chapter 2.2 --- VLSI Design Cycle [1] --- p.6 / Chapter 2.2.1 --- System Specification --- p.6 / Chapter 2.2.2 --- Architectural Design --- p.6 / Chapter 2.2.3 --- Functional Design --- p.6 / Chapter 2.2.4 --- Logic Design --- p.8 / Chapter 2.2.5 --- Circuit Design --- p.8 / Chapter 2.2.6 --- Physical Design --- p.8 / Chapter 2.2.7 --- Fabrication --- p.8 / Chapter 2.2.8 --- Packaging and Testing --- p.9 / Chapter 2.3 --- Physical Design Cycle [1] --- p.9 / Chapter 2.3.1 --- Partitioning --- p.9 / Chapter 2.3.2 --- Floorplanning and Placement --- p.11 / Chapter 2.3.3 --- Routing --- p.11 / Chapter 2.3.4 --- Compaction --- p.12 / Chapter 2.3.5 --- Extraction and Verification --- p.12 / Chapter 2.4 --- Chapter Summary --- p.12 / Chapter 3 --- Recent Approaches on Circuit Partitioning --- p.14 / Chapter 3.1 --- Preliminaries --- p.14 / Chapter 3.2 --- Circuit Representation --- p.15 / Chapter 3.3 --- Delay Modelling --- p.16 / Chapter 3.4 --- Partitioning Objectives --- p.19 / Chapter 3.4.1 --- Interconnections between Partitions --- p.19 / Chapter 3.4.2 --- Delay Minimization --- p.19 / Chapter 3.4.3 --- Area and Number of Partitions --- p.20 / Chapter 3.5 --- Partitioning Algorithms --- p.20 / Chapter 3.5.1 --- Cut-size Driven Partitioning Algorithm --- p.21 / Chapter 3.5.2 --- Delay Driven Partitioning Algorithm --- p.32 / Chapter 3.5.3 --- Acyclic Circuit Partitioning Algorithm --- p.33 / Chapter 4 --- Clustering Based Acyclic Multi-way Partitioning --- p.38 / Chapter 4.1 --- Preliminaries --- p.38 / Chapter 4.2 --- Previous Works on Clustering Based Partitioning --- p.39 / Chapter 4.2.1 --- Multilevel Circuit Partitioning [2] --- p.40 / Chapter 4.2.2 --- Cluster-Oriented Iterative-Improvement Partitioner [3] --- p.42 / Chapter 4.2.3 --- Section Summary --- p.44 / Chapter 4.3 --- Problem Formulation --- p.45 / Chapter 4.4 --- Clustering Based Acyclic Multi-Way Partitioning --- p.46 / Chapter 4.5 --- Modified Fan-out Free Cone Decomposition --- p.47 / Chapter 4.6 --- Clustering Phase --- p.48 / Chapter 4.7 --- Partitioning Phase --- p.51 / Chapter 4.8 --- The Acyclic Constraint --- p.52 / Chapter 4.9 --- Experimental Results --- p.57 / Chapter 4.10 --- Chapter Summary --- p.58 / Chapter 5 --- Network Flow Based Multi-way Partitioning --- p.61 / Chapter 5.1 --- Preliminaries --- p.61 / Chapter 5.2 --- Notations and Definitions --- p.62 / Chapter 5.3 --- Net Modelling --- p.63 / Chapter 5.4 --- Previous Works on Network Flow Based Partitioning --- p.64 / Chapter 5.4.1 --- Network Flow Based Min-Cut Balanced Partitioning [4] --- p.65 / Chapter 5.4.2 --- Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs [5] --- p.66 / Chapter 5.5 --- Proposed Net Modelling --- p.70 / Chapter 5.6 --- Partitioning Properties Based on the Proposed Net Modelling --- p.73 / Chapter 5.7 --- Partitioning Step --- p.75 / Chapter 5.8 --- Constrained FM Post Processing Step --- p.79 / Chapter 5.9 --- Experiment Results --- p.81 / Chapter 6 --- Conclusion --- p.86 / Bibliography --- p.88

There is an emerging need to develop new techniques for control system design that better address the challenges posed by modern large-scale cyber-physical systems. These systems are often massive networks of interconnected and interoperating subsystems that fuse physical processes, embedded computation, automation technologies, and communication. The resulting problems are dimensionally large, exhibit significant time-varying structural variations during operation, and feature complex dynamics, constraints and objectives across local and global-system scales. These properties are difficult to address using traditional control theoretic methods without substantial loss of performance and robustness. To overcome these limitations, this dissertation presents new concepts and methods for control of modern large-scale variably-structured systems through self-assembling and self-configuring control constructs that allow for fundamental restructuring of the control system’s topology in response to the current system structure. We present the System Component Graph (SCG) formulation as a mathematical framework that generalizes and extends directed graph methods from decentralized control. We present algorithms, methods, and metrics for real-time decentralization and control-structure optimization, utilizing the inclusion principle for addressing interconnected overlapping dynamics and optimal linear-quadratic (LQ) methods for local decentralized subsystem control. Global system control and performance is achieved through a centralized planner that provides continuous real-time optimized trajectories as guidance command inputs to each subsystem. We present the method of Random Subcomplement Trees (RST) for pseudo-optimal real-time trajectory planning of large-scale systems which formalizes and extends the method of rapidly-exploring random trees in a control optimization framework. The RST method defines transformations from the higher-dimension state space into an intermediate lower-dimensional search space, where optimal transitions between subspace states are defined. In the context of this approach, the resulting decentralized topology found within the SCG framework provides the RST subspace definition and requisite transformations, and optimal transitions in the search space are found through forward evaluation of the closed-loop decentralized subsystem dynamics. The methods developed in this thesis are applied to a set of real-world problems spanning various domains and demonstrate the application of these methods from first-principle modeling through control system analysis, design, implementation, and evaluation in experimental tests and simulation.

Higher performance, lower cost, increasingly minimizing integrated circuit components, and higher packaging density of chips are ongoing goals of the microelectronic and computer industry. As these goals are being achieved, however, power consumption and flexibility are increasingly becoming bottlenecks that need to be addressed with the new technology in Very Large-Scale Integrated (VLSI) design. For modern systems, more energy is required to support the powerful computational capability which accords with the increasing requirements, and these requirements cause the change of standards not only in audio and video broadcasting but also in communication such as wireless connection and network protocols. Powerful flexibility and low consumption are repellent, but their combination in one system is the ultimate goal of designers. A generic domain-specific low-power reconfigurable processor for the distributed arithmetic algorithm is presented in this dissertation. This domain reconfigurable processor features high efficiency in terms of area, power and delay, which approaches the performance of an ASIC design, while retaining the flexibility of programmable platforms. The architecture not only supports typical distributed arithmetic algorithms which can be found in most still picture compression standards and video conferencing standards, but also offers implementation ability for other distributed arithmetic algorithms found in digital signal processing, telecommunication protocols and automatic control. In this processor, a simple reconfigurable low power control unit is implemented with good performance in area, power and timing. The generic characteristic of the architecture makes it applicable for any small and medium size finite state machines which can be used as control units to implement complex system behaviour and can be found in almost all engineering disciplines. Furthermore, to map target applications efficiently onto the proposed architecture, a new algorithm is introduced for searching for the best common sharing terms set and it keeps the area and power consumption of the implementation at low level. The software implementation of this algorithm is presented, which can be used not only for the proposed architecture in this dissertation but also for all the implementations with adder-based distributed arithmetic algorithms. In addition, some low power design techniques are applied in the architecture, such as unsymmetrical design style including unsymmetrical interconnection arranging, unsymmetrical PTBs selection and unsymmetrical mapping basic computing units. All these design techniques achieve extraordinary power consumption saving. It is believed that they can be extended to more low power designs and architectures. The processor presented in this dissertation can be used to implement complex, high performance distributed arithmetic algorithms for communication and image processing applications with low cost in area and power compared with the traditional methods.

Doctor of Philosophy / Department of Horticulture and Natural Resources / Jack Fry / Megan Kennelly / Zoysiagrasses (Zoysia spp.) use C4 metabolism and are more drought resistant than C3 grasses. However, the long dormancy period between autumn and spring limits the use of zoysiagrass by homeowners and professional turfgrass managers. In addition, large patch has become the primary pest on zoysiagrass, and improved cultivars with good cold hardiness and large patch resistance are needed in the transition zone. Tall fescue (Schedonorus arundinaceus Schreb), a C3 grass, is used frequently in Kansas due to its heat and drought tolerance compared to some other C3 grasses. However, brown patch (Rhizoctonia solani) is the main disease limiting its growth in summer. Alternatively, mixing zoysiagrass with tall fescue may help reduce brown patch incidence. The objective of these projects were to: (1) evaluate methods for establishing a perennial mixture of seeded zoysiagrass and tall fescue; (2) determine whether a zoysiagrass/ tall fescue polystand is less susceptible to brown patch and results in improved summer quality compared to a tall fescue monostand; and (3) evaluate experimental zoysiagrass genotypes to identify one or more potential new cultivars which have high quality and tolerance to cold and large patch. I found that polystands of zoysiagrass and tall fescue were most successfully established by seeding zoysiagrass at 49 kg ha-1 in June and tall fescue at 392 kg ha-1 in September into the established zoysiagrass sward. Polystand establishment was also superior at a 1.9 cm mowing height than a 5.1 cm mowing height. The resulting mixture resulted in improved turf color in late fall and early spring compared to a zoysiagrass monostand. In addition, using a zoysiagrass-tall fescue polystand reduced brown patch by up to 21% compared to a tall fescue monostand. In the zoysiagrass breeding project, I identified ten progeny out of sixty evaluated that had better tolerance to large patch (up to 40 % less plot area affected) and better quality compared to Meyer zoysiagrass, which is the standard cultivar used in the transition zone.

Aero-engine intakes play a critical role in the performance of modern high-bypass turbofan engines. It is their function to provide uniformly distributed, steady air flow to the engine fan face under a variety of flow conditions. However, during situations of high incidence, high curvature of the intake lip can accelerate flow to supersonic speeds, terminating with a shock wave. This produces undesirable shock wave boundary layer interactions (SWBLIs). Reynolds-Averaged Navier Stokes (RANS) turbulence models have been shown to be insensitive to the effects of boundary layer relaminarisation present in these highly-accelerated flows. Further, downstream of the SWBLI, RANS methods fail to capture the distorted flow that propagates towards the engine fan face. The present work describes simulations of a novel experimental intake rig model that replicates the key physics found in a real intake- namely acceleration, shock and SWBLI. The model is a simple geometric configuration resembling a lower intake lip at incidence. Simulations are carried out at two angles of attack, $\alpha=23^{\circ}$ and $\alpha=25^{\circ}$, with the more aggressive $\alpha=25^{\circ}$ possessing a high degree of shock oscillation. RANS, Large Eddy Simulations (LES) and hybrid RANS-LES are carried out in this work. Modifications to the one-equation Spalart-Allmaras (SA) RANS turbulence model are proposed to account for the effects of re-laminarisation and curvature. The simulation methods are validated against two canonical test cases. The first is a subsonic hump model where RANS modifications give a noticeable improvement in surface pressure predictions, even for this mild acceleration case. However, RANS is shown to over-predict the separation size. LES performs much better here, as long as the Smagorinsky-Lilly SGS model is not used. The $\sigma$-SGS model is found to perform best, and is used to run a hybrid RANS-LES that predicts a separation bubble size within $4\%$ of LES. The second canonical test case is a transonic hump that features a normal shockwave and SWBLI. RANS performs well here, predicting shock location, surface pressure and separation with good agreement with experimental measurements. Hybrid RANS-LES also performs well, but predicts a shock downstream of that measured by experiment. The use of an improved shock sensor here is able to maintain solution accuracy. Simulations of the intake rig are then run. RANS modifications provide a significant improvement in prediction of the shock location and lip surface pressure compared to the standard SA model. However, RANS models fail to reproduce the post shock interaction flow well, giving incorrect shape of the flow distortion. Further, RANS is inherently unable to capture the unsteady shock oscillations and related flow features. LES and hybrid RANS-LES predict the shock location and SWBLI well, with the downstream flow distortion also in very good agreement with experimental measurements. LES and hybrid RANS-LES are able to reproduce the time averaged smearing of the shock which RANS cannot. However, shock oscillations in the $\alpha=25^{\circ}$ case present a particular challenge for costly LES, requiring long simulation time to obtain time averaged flow statistics. Hybrid RANS-LES offers a significant saving in computational expense, costing approximately $20\%$ of LES. The work proposes recommendations for simulation strategy for intakes at incidence based on computational cost and performance of simulation methods.

Li, Liang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves 57-61). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.1.1 --- Partitioning --- p.1 / Chapter 1.1.2 --- Floorplanning and Placement --- p.2 / Chapter 1.1.3 --- Routing --- p.2 / Chapter 1.1.4 --- Compaction --- p.3 / Chapter 1.2 --- Motivations --- p.3 / Chapter 1.3 --- Problem Formulation --- p.4 / Chapter 1.3.1 --- Properties of OARSMT --- p.4 / Chapter 1.4 --- Progress on the Problem --- p.4 / Chapter 1.5 --- Contributions --- p.5 / Chapter 1.6 --- Thesis Organization --- p.6 / Chapter 2 --- Literature Review on OARSMT --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Previous Methods --- p.9 / Chapter 2.2.1 --- OARSMT --- p.9 / Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13 / Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14 / Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14 / Chapter 2.3 --- Comparison --- p.15 / Chapter 3 --- Heuristic Method --- p.17 / Chapter 3.1 --- Introduction --- p.17 / Chapter 3.2 --- Our Approach --- p.18 / Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18 / Chapter 3.2.2 --- Propagation --- p.20 / Chapter 3.2.3 --- Backtrack --- p.23 / Chapter 3.2.4 --- Finding MST --- p.26 / Chapter 3.2.5 --- Local Refinement Scheme --- p.26 / Chapter 3.3 --- Experimental Results --- p.28 / Chapter 3.4 --- Summary --- p.28 / Chapter 4 --- Exact Method --- p.32 / Chapter 4.1 --- Introduction --- p.32 / Chapter 4.2 --- Review on GeoSteiner --- p.33 / Chapter 4.3 --- Overview of our Approach --- p.33 / Chapter 4.4 --- FST with Virtual Pins --- p.34 / Chapter 4.4.1 --- Definition of FST --- p.34 / Chapter 4.4.2 --- Notations --- p.36 / Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36 / Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46 / Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46 / Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48 / Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50 / Chapter 4.7 --- Experimental Results --- p.52 / Chapter 4.8 --- Summary --- p.53 / Chapter 5 --- Conclusion --- p.55 / Bibliography --- p.61

Ma, Tilen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 98-100). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 0.1 --- Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design Cycle --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.11 / Chapter 1.4 --- Organization of the Thesis --- p.13 / Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16 / Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18 / Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20 / Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23 / Chapter 2.5.1 --- Representation of Placement Constraints --- p.23 / Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24 / Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25 / Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Previous Work --- p.28 / Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28 / Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32 / Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Transitive Closure Graph [6] --- p.39 / Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41 / Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44 / Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45 / Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45 / Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46 / Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48 / Chapter 5.1 --- Motivation --- p.48 / Chapter 5.2 --- Problem Formulation --- p.49 / Chapter 5.3 --- Methodology --- p.50 / Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51 / Chapter 5.3.2 --- Construction of Common Graph --- p.52 / Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53 / Chapter 5.3.4 --- Formation of Bus Components --- p.55 / Chapter 5.3.5 --- Bus Feasibility Check --- p.56 / Chapter 5.3.6 --- Overlap Removal --- p.57 / Chapter 5.3.7 --- Floorplan Realization --- p.58 / Chapter 5.3.8 --- Simulated Annealing --- p.58 / Chapter 5.3.9 --- Soft Module Adjustment --- p.60 / Chapter 5.4 --- Experimental Results --- p.60 / Chapter 5.5 --- Summary --- p.65 / Chapter 6 --- Conclusion --- p.67 / Chapter A --- Appendix --- p.69 / Chapter A.1 --- Well-Known Algorithms --- p.69 / Chapter A.1.1 --- Kruskal's Algorithm --- p.69 / Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69 / Chapter A.2 --- Figures of Resulting Floorplans --- p.71 / Chapter A.2.1 --- Data Set One --- p.71 / Chapter A.2.2 --- Data Set Two --- p.80 / Chapter A.2.3 --- Data Set Three --- p.85 / Chapter A.2.4 --- Data Set Four --- p.92 / Bibliography --- p.98