Single-walled carbon nanotubes (SWNTs), with their superior combination of electrical and mechanical properties, have drawn attention from many researchers for potential applications in electronics. Many SWNT-based electronic device prototypes have been developed including transistors, interconnects and flexible electronics. In this thesis, a fabrication method for patterned SWNT networks and devices based on colloidal lithography is presented. Patterned SWNT networks are for the first time formed via solution deposition on a heterogeneous surface. This method demonstrates a simple and straight-forward way to fabricate SWNT networks in a controllable manner. Colloidal sphere monolayers were obtained by drop-casting from solution onto clean substrates. The colloidal monolayer was utilized as a mask for the fabrication of patterned SWNT networks. SWNT networks were shown to be patterned either by depositing SWNT solutions on top of a colloidal monolayer or by depositing a mixed SWNT-colloidal sphere aqueous suspension on the substrates. Colloidal monolayers were examined by optical microscopy and it was found that the monolayer quality can be affected by the concentration of colloids in solution. Polystyrene colloidal solution with concentration of 0.02 wt% ~ 0.04 wt % was found optimal for maximum coverage of colloidal monolayers on SiO2 substrates. After removing the colloidal spheres, the topology of the patterned SWNT networks was characterized by atomic force microscopy and scanning electron v microscopy. Two-dimensional ordered arrays of SWNT rings and SWNTs interconnecting the SWNT rings were observed in the resulting network structure. The height of the rings was about 4-10 nm and the diameter was about 400 nm. In some samples, mesh-like patterned SWNT networks are also observed. It is hypothesized that the capillary forces induced by Van der Waals interaction at liquid/air/solid interfaces play an important role during the formation of the patterned SWNT networks. Raman spectroscopy was also employed to identify the chirality and diameter of the SWNTs in the networks. Both metallic and semiconducting SWNTs were found in the networks and the diameter of the SWNTs was about 1 to 2 nm. The electrical properties of SWNT networks, including random SWNT networks, partially patterned SWNT networks and fully patterned SWNT networks were characterized by a probe station and a Keithley 4200 semiconductor measurement system. The random SWNT networks had two-terminal resistance varying between several MΩ to several hundred MΩ. Field effect behavior was observed in some devices with relatively high resistance and nonlinear I-V curves. Those devices had on/off ratio of less than 100. There was significant leakage current in the ―off‖ state likely due to metallic tube pathways in the networks. The partially patterned SWNT networks had resistance that varied from 20 KΩ to 10 MΩ, but did not display field effect behavior in our studies. The resistance of the patterned SWNT networks was about 10 MΩ - 100 MΩ. The electrical characteristics of the patterned SWNT networks as thin film transistors were investigated, and the on/off ratio of the devices varied from 3 to 105. The upper limit of mobility in the devices was about ~ 0.71 – 5 cm2/V·s. The subthreshold slope of patterned SWNT network FETs can be as low as 210 meV/dec. / Graduate / 0544

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes.

Thesis (doctoral)--Humboldt-Universiẗat, Berlin, 2007. / Mixed media. Includes bibliographical references (p. 273-298) and index.

Thesis (doctoral)--Technische Universiteit Delft, 1991. / Summary in Dutch. "Stellingen" ([1] folded leaf) inserted. Vita. Includes bibliographical references (p. BR-1-BR-15).

Thesis (Ph. D.)--School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, 2005. Directed by Clifford L. Henderson. / Brent Carter, Committee Member ; Clifford L. Henderson, Committee Chair ; Dennis Hess, Committee Member ; Peter Ludovice, Committee Member ; Kevin Martin, Committee Member. Vita. Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 55-57).

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Thomas K. Gaylord; Committee Member: Donald D. Davis; Committee Member: Gee-Kung Chang; Committee Member: Muhannad S. Bakir; Committee Member: Phillip N. First. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M.S.)--Rochester Institute of Technology, 2005. / Typescript. Includes bibliographical references (leaves 89-94).

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Microelectronic fabrication of Si typically involves high-temperature or high-energy processes. For instance, wafer fabrication, transistor fabrication, and silicidation are all above 500°C. Contrary to that tradition, we believe low-energy processes constitute a better alternative to enable the industrial application of single-molecule devices based on 2D materials. The present work addresses the postsynthesis processing of graphene at unconventional low temperature, low energy, and low pressure in the poly methyl-methacrylate- (PMMA-) assisted transfer of graphene to oxide wafer, in the electron-beam lithography with PMMA, and in the plasma patterning of graphene with a PMMA ribbon mask. During the exposure to the oxygen plasma, unprotected areas of graphene are converted to graphene oxide. The exposure time required to produce the ribbon patterns on graphene is 2 minutes. We produce graphene ribbon patterns with ∼50 nm width and integrate them into solid state and liquid gated transistor devices. / )e submitted manuscript has been created by UChicago Argonne, LLC, Operator of Argonne National Laboratory (“Argonne”). Argonne, a U.S. Department of Energy Office of Science laboratory, is operated under Contract DE-AC02-06CH11357. )e U.S. Government retains for itself, and others acting on its behalf, a paid-up nonexclusive, irrevocable worldwide license in said article to reproduce, prepare derivative works, distribute copies to the public, and perform publicly and display publicly, by or on behalf of the government. Funding text #2 )e Center for Nanoscale Materials was supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract DE-AC02-06CH11357. )e authors also acknowledge financial support from Argonne National Laboratory’s Laboratory-Directed Research and Development Strategic Initiative. / Revisión por pares