There are a significant number of microwave applications, where improvement of such qualities as manufacturing costs, size, weight, power consumption, etc. have attracted much research interest. In order to meet these requirements, new technologies can be actively involved in fabrication of microwave components with improved characteristics. One such fabrication technology is called LIGA (a German acronym with an English translation of lithography, electroforming, and moulding) that allows fabrication of high aspect ratio (tall) structures, and only recently is receiving growing attention in microwave component fabrication.<p> The characteristics of high aspect ratio microstrip and coplanar waveguide (CPW) transmission lines are investigated in this thesis. Very low impedance high aspect ratio CPW transmission lines can be realized. A high aspect ratio microstrip folded half wavelength open loop resonator is introduced. Effective configurations for external and bypass gap coupling with open loop resonators are given. Filters with transmission zeros in the stopband, consisting of high aspect ratio single mode open loop resonators are presented to demonstrate the advantages of high aspect ratio structures in realizing lower external quality factors or tight coupling. The transmission zeros are created by novel coupling routings. Some of the filters are fabricated and the filter responses are measured to validate high aspect ratio coupling structures. High aspect ratio diplexers with increased channel isolation are also designed by appropriately combining filters with transmission zeros.<p> A wideband bandpass filter design method, based on the electromagnetic bandgap (EBG) concept is introduced in this thesis. The wideband filters are miniaturized as a result of using the EBG concept in design. An EBG based wideband filter consisting of unit cells that are realized by using high aspect ratio CPW stepped impedance resonators is also presented. The main advantage of this approach is that the high aspect ratio CPW structures make short unit cells practically realizable, resulting in compact filter structure.

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Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes.

Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.<p>In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.<p>The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.<p>This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design.

There are a significant number of microwave applications, where improvement of such qualities as manufacturing costs, size, weight, power consumption, etc. have attracted much research interest. In order to meet these requirements, new technologies can be actively involved in fabrication of microwave components with improved characteristics. One such fabrication technology is called LIGA (a German acronym with an English translation of lithography, electroforming, and moulding) that allows fabrication of high aspect ratio (tall) structures, and only recently is receiving growing attention in microwave component fabrication.<p> The characteristics of high aspect ratio microstrip and coplanar waveguide (CPW) transmission lines are investigated in this thesis. Very low impedance high aspect ratio CPW transmission lines can be realized. A high aspect ratio microstrip folded half wavelength open loop resonator is introduced. Effective configurations for external and bypass gap coupling with open loop resonators are given. Filters with transmission zeros in the stopband, consisting of high aspect ratio single mode open loop resonators are presented to demonstrate the advantages of high aspect ratio structures in realizing lower external quality factors or tight coupling. The transmission zeros are created by novel coupling routings. Some of the filters are fabricated and the filter responses are measured to validate high aspect ratio coupling structures. High aspect ratio diplexers with increased channel isolation are also designed by appropriately combining filters with transmission zeros.<p> A wideband bandpass filter design method, based on the electromagnetic bandgap (EBG) concept is introduced in this thesis. The wideband filters are miniaturized as a result of using the EBG concept in design. An EBG based wideband filter consisting of unit cells that are realized by using high aspect ratio CPW stepped impedance resonators is also presented. The main advantage of this approach is that the high aspect ratio CPW structures make short unit cells practically realizable, resulting in compact filter structure.

Electron beam lithography is gaining widespread utilization as the semiconductor industry progresses towards both advanced optical and non-optical lithographic technologies for high resolution patterning. The current resist technologies are based on organic systems that are imaged most commonly through chain scission, networking, or a chemically amplified polarity change in the material. Alternative resists based on inorganic systems were developed and characterized in this research for high resolution electron beam lithography and their interactions with incident electrons were investigated using Monte Carlo simulations. A novel inorganic resist imaging scheme was developed using metal-organic precursors which decompose to form metal oxides upon electron beam irradiation that can serve as inorganic hard masks for hybrid bilayer inorganic-organic imaging systems and also as directly patternable high resolution metal oxide structures. The electron beam imaging properties of these metal-organic materials were correlated to the precursor structure by studying effects such as interactions between high atomic number species and the incident electrons. Optimal single and multicomponent precursors were designed for utilization as viable inorganic resist materials for sub-50nm patterning in electron beam lithography. The electron beam imaging characteristics of the most widely used inorganic resist material, hydrogen silsesquioxane (HSQ), was also enhanced using a dual processing imaging approach with thermal curing as well as a sensitizer catalyzed imaging approach. The interaction between incident electrons and the high atomic number species contained in these inorganic resists was also studied using Monte Carlo simulations. The resolution attainable using inorganic systems as compared to organic systems can be greater for accelerating voltages greater than 50 keV due to minimized lateral scattering in the high density inorganic systems. The effects of loading nanoparticles in an electron beam resist was also investigated using a newly developed hybrid Monte Carlo approach that accounts for multiple components in a solid film. The resolution of the nanocomposite resist process was found to degrade with increasing nanoparticle loading. Finally, the electron beam patterning of self-assembled monolayers, which were found to primarily utilize backscattered electrons from the high atomic number substrate materials to form images, was also investigated and characterized. It was found that backscattered electrons limit the resolution attainable at low incident electron energies.

As semiconductor technology advances into the nano-scale era and more functional blocks are added into systems on chip (SoC), the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit performance degradation comes from deterministic within-die variation from lithography imperfections and Cu interconnect chemical mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, a new analysis tool is required. Thus a methodology has been proposed to involve layout-dependent within-die variations in static timing analysis. The methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation. Also, this thesis presents a methodology to generate test sets to diagnose the sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to physical mechanisms and to distinguish among different sources of within-die variation. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose lithography-caused delay faults. The effectiveness in diagnosis is evaluated for ISCAS85 benchmark circuits.

In this thesis, we used the E-Beam lithography to fabricate a device of coupled microdisk-ring laser on the sample which was grown by molecular beam epitaxy (MBE), and analyzed the coupled effect of the device. The active layer was composed of six compressively strained InGaAs quantum dots (QDs) that were designed to support gain at 1200nm. Under the active layer, we replaced sacrificial layer by distributed bragg reflector (DBR). The purpose of the DBR was used like a mirror to reflect the particular wavelength which located at DBR¡¦s stop band, so the energy would be confined in the active layer. The device was composed of a microdisk and a ring. The diameter of the microdisk was 3£gm, and the width of the ring is 250nm. The microdisk was placed in the ring, and the gap of both was 100nm. After design, we simulated whether the device could generate coupled modes by Finite-Difference Time-Domain (FDTD). In experiment, we used the E-Beam lithography to define negative pattern on the sample which is spread with the PMMA. We also used the thermal evaporation to evaporate the metal, and lift the metal to form our pattern. Finally, we used the dry etching to transform the pattern to the epitaxial layer, and then the device was completed. In measurement, we used the micro-PL to measure our device, and got a successful result. The result showed our device generated eight resonant modes. The measured result matched the simulation result. Through simulation, the device generated three coupled modes, 1173.8nm, 1206nm, and 1214nm. We expect that the device will be used to generate terahertz source in the future.

In this thesis, we fabricate the quantum dots (QDs) micro-pillar of metal-coated by E-beam lithography, and analyze the optical and electrical properties of micro-pillar cavity devices. For the sample materials, we use S-K mode to grow 3-layer In0.75Ga0.25As QDs structures sandwiched by up and down Al0.5Ga0.5As cladding layer on GaAs substrate by molecular-beam epitaxy (MBE). 40nm GaAs spacer layers with 2nm p-modulation doping in the central barrier are adopted in this study. The micro-pillar with diameter of 2 m, metal coated on top (p-type) and down (n-type) facet are designed. The good reflectivities of metal contacts provide more energy extraction inside the cavity. We expect the device lasing while the current injection. First, we design the morphology and size of patterns by AutoCAD software. Then, we use e-beam lithography with proper exposure condition to define the patterns, and thermal evaporation to deposit metals. The superfluous metal is lifted off and the defined area metal is served as dry etching mask to transfer the pattern to the dielectric layer and epi-layer. Finally, we use SiO2 layer to prevent current leakage, and the p-n contact on each facet to complete the devices. Micro-pillar samples with/without metal coated are analyzed by micro-PL system. The emission wavelength of 1282nm and the calculated Q-value of 100 are obtained for the sample with metal coated, an increase of 500%. From the EL measurement results, the device of micro-pillar samples with metal coated generate three peaks, 1149nm, 1221nm and 1291nm. Besides, it can efficiently improve the emission intensities. The measured result matched the simulation result.

Abstract Negative index structures could be implemented through surface Plasmon polariton waves generated by nanostructures. We are interested in PMMA grating structure on curved metal surface. In order to fabricate this kind of samples, a series process parameters have been tested and also the lift-off process has been developed. Our results show superlens effect under optical microscope(OM). The sub-wavelength grating image is reconstructed in the non-grating region where the PMMA dielectric layer is not uniform. Surface Plasmon(SPP) waves generated in the grating region propagate to the non-grating region and are scattered out through the non-uniform PMMA layer. The grating information is not resolvable under OM but clear in the reconstructed region. It shows that SPP waves can show super resolution and a simple batch process should be developed in the future.