by Chung-Yuk Or. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 95-[98]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Fully Differential CMOS Operational Amplifier Design --- p.4 / Chapter 2.1 --- Wide-Swing Current Mirror --- p.5 / Chapter 2.2 --- Wide-Swing Biasing Network --- p.8 / Chapter 2.3 --- Fully differential folded-cascode operational amplifier --- p.13 / Chapter 2.3.1 --- Small-Signal Analysis --- p.16 / Chapter 2.4 --- Gain-boost technique --- p.18 / Chapter 2.4.1 --- Frequency Response --- p.24 / Chapter 2.5 --- Common-Mode Feedback Network --- p.26 / Chapter 2.5.1 --- Continuous-Time CMFB Circuit --- p.27 / Chapter 2.5.2 --- Discrete-Time CMFB circuit --- p.33 / Chapter 2.6 --- Design Flow of the Operational Amplifier --- p.35 / Chapter 3 --- Physical Design of the Operational Amplifier --- p.39 / Chapter 3.1 --- Layout Level Design --- p.40 / Chapter 3.2 --- Layout Techniques --- p.42 / Chapter 3.3 --- Input Protection Circuitry --- p.47 / Chapter 4 --- Simulation Results --- p.49 / Chapter 4.1 --- Simulation of the Operational Amplifier --- p.49 / Chapter 4.2 --- Simulation of Auxiliary Amplifiers --- p.57 / Chapter 4.3 --- Simulation of the Common-Mode Feedback Circuit --- p.62 / Chapter 5 --- Measurement Results --- p.70 / Chapter 5.1 --- Transient Response Measurement --- p.70 / Chapter 5.2 --- Frequency Response Measurement --- p.74 / Chapter 5.3 --- Power Consumption Measurement --- p.78 / Chapter 5.4 --- Performance Evaluation --- p.81 / Chapter 6 --- Layout Driven Operational Amplifiers Macromodelling --- p.82 / Chapter 6.1 --- Motivations --- p.83 / Chapter 6.2 --- Methodology --- p.84 / Chapter 6.3 --- Macromodelling the operational amplifier --- p.85 / Chapter 6.4 --- Simulation Results --- p.88 / Chapter 6.5 --- Conclusions --- p.92 / Chapter 7 --- Conclusions --- p.93 / Bibliography --- p.95 / A Layout Diagrams and Chip Micrograph --- p.99

Tang, Xian. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

在過去的十年裡，隨著便攜式通訊，電腦與消費電子市場的快速發展，以及在超大規模積體電路中，越來越多的功能實現被轉移到數字領域中，這些都引起了人們對模數轉換器研究的極大關注。 / 基於過採樣與量化誤差整形技術，ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而，爲了優化其在功耗，硅片面積與上市時間等方面的性能，ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新，包括算法，架構及電路設計，從而提升其在通訊，語音與傳感等應用領域中的性能指標。 / 本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號，自鏡像信號及量化噪聲混疊至輸入信道，從而降低模數轉換器的動態範圍。為此，本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器，比較器與數模轉換器，芯片的面積得到了大幅的降低。基於以上技術，在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片，其鏡像抑制比可達到73dB，這是迄今為止公開發表論文中報告的最高值。 / 在本文的第二部份，我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而，相比于單環型，級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感，因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此，我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術，我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外，本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術，相關雙採用技術，反混疊濾波，噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明，採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。 / 本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中，由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時，這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明，其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內，使得電容-數字轉換器在單端電容傳感模式下的線性度（準確度）從9.3位提高至12.3位；在差分電容傳感模式下的線性度（準確度）從10.1位提高至13.3位。最後，本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。 / The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design. / Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on. / First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported. / Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB. / Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Bing. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese. / Abstracts of thesis entitled: --- p.I / 摘 要 --- p.V / Contents --- p.VII / List of Figures --- p.XI / List of Tables --- p.XVI / Acknowledgement --- p.XVII / Chapter CHAPTER 1. --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Original contributions and outline of the thesis --- p.2 / References --- p.1 / Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3 / Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6 / Chapter 2.2 --- Mismatches in QBDSM --- p.8 / Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13 / Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13 / Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19 / Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20 / Chapter 2.3.4 --- Summary and Simulation Results --- p.27 / Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34 / Chapter 2.5 --- Measurement Results Analysis --- p.40 / Chapter 2.6 --- Conclusions --- p.47 / Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48 / Chapter A. --- I/Q Mismatch in Mixer --- p.48 / Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49 / Chapter C. --- I/Q Mismatch in QBDSM --- p.50 / Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51 / Chapter APPENDIX II: --- IRR Measurement Method --- p.52 / References --- p.56 / Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59 / Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61 / Chapter 3.1.1 --- Integrator Gain Error --- p.64 / Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65 / Chapter 3.1.3 --- Modulator Architecture --- p.66 / Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68 / Chapter 3.1.5 --- Noise Analysis --- p.69 / Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71 / Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73 / Chapter 3.2.2 --- Simulation Results --- p.75 / Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76 / Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77 / Chapter 3.3.2 --- Behavorial Simulation Results --- p.79 / Chapter 3.4 --- Jitter Analysis --- p.80 / Chapter 3.4.1 --- Jitter on Rising Edges --- p.81 / Chapter 3.4.2 --- Duty cycle jitter --- p.84 / Chapter 3.5 --- Prototyping Modulator Design --- p.85 / Chapter 3.6 --- Measurement Results --- p.89 / Chapter 3.7 --- Summary --- p.95 / References --- p.97 / Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105 / Chapter 4.1 --- Introduction --- p.105 / Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107 / Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107 / Chapter 4.2.2 --- Differential Sensing Mode --- p.111 / Chapter 4.3 --- Circuit Implementation --- p.114 / Chapter 4.4 --- Measurement Results --- p.117 / Chapter 4.5 --- Conclusion --- p.125 / Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126 / References --- p.127 / Chapter CHAPTER 5. --- Conclusions and future works --- p.129 / Chapter 5.1 --- Conclusions --- p.129 / Chapter 5.2 --- Future works --- p.130 / Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131

With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions ever-so-close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern-day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On-chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully-integrated system for on-chip combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated test transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the under- lying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry.

Chi-Hong, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 114-117). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Table of Contents --- p.vi / List of Figures --- p.x / List of Tables --- p.xiii / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- System on a Chip (SoC) Design Challenges --- p.1 / Chapter 1.2. --- Research Objective --- p.3 / Chapter 1.3. --- Thesis Organization --- p.3 / Chapter 2. --- Fundamentals of CMOS Current Mode A/D converters --- p.5 / Chapter 2.1. --- Overview --- p.5 / Chapter 2.2. --- Current Mode Signal Processing --- p.5 / Chapter 2.2.1. --- Voltage Mode Circuit Design Technique --- p.5 / Chapter 2.2.2. --- Current Mode Circuit Design Technique --- p.6 / Chapter 2.2.3. --- First Generation (FG) SI Memory Cell vs. Second Generation (SG) SI Memory Cell --- p.7 / Chapter 2.3. --- Ideal Nyquist Rate A/D converters --- p.9 / Chapter 2.4. --- Static Performance Parameters --- p.13 / Chapter 2.4.1. --- Differential Non-Linearity (DNL) --- p.13 / Chapter 2.4.2. --- Integral Non-Linearity (INL) --- p.13 / Chapter 2.5. --- Performance Parameters in Frequency Domain --- p.15 / Chapter 2.5.1. --- Signal-to-Noise and Distortion Ratio (SNDR) --- p.16 / Chapter 2.5.2. --- Effective Number of Bits (ENOB) --- p.16 / Chapter 2.5.3. --- Spurious Free Dynamic Range (SFDR) --- p.16 / Chapter 3. --- Proposed Current Mirror Memory Cell (CMMC) --- p.18 / Chapter 3.1. --- Overview --- p.18 / Chapter 3.2. --- Working Principle of CMMC --- p.18 / Chapter 3.3. --- CMMC vs. FG SI Cells --- p.20 / Chapter 3.4. --- Analog Delay Cell Implementation using the two kinds of memory cells --- p.21 / Chapter 3.4.1. --- Delay Cell Implementation by FG Memory Cells --- p.22 / Chapter 3.4.2. --- Delay Cell Implementation by CMMC --- p.23 / Chapter 3.4.3. --- Simulation Results --- p.24 / Chapter 3.5. --- Conclusion --- p.27 / Chapter 4. --- Architectural Design of the 12-Bit CMOS A/D Converter --- p.28 / Chapter 4.1. --- Overview --- p.28 / Chapter 4.2. --- The Floating Analog-to-Digital Converter --- p.28 / Chapter 4.3. --- Conversion Algorithm --- p.32 / Chapter 4.4. --- Accuracy Considerations Due to Circuit Non-Idealities --- p.34 / Chapter 4.4.1. --- Gain Error of Residual Generator --- p.34 / Chapter 4.4.2. --- Offset Error of Residual Generator --- p.36 / Chapter 4.5. --- Speed Consideration --- p.36 / Chapter 4.6. --- Power Consumption vs. No. of Bits per Stage --- p.38 / Chapter 4.7. --- Final Architectural Design --- p.40 / Chapter 5. --- A/D Converter Implementation using CMMC --- p.41 / Chapter 5.1. --- Overview --- p.41 / Chapter 5.2. --- Current Sample-and-Hold --- p.41 / Chapter 5.2.1. --- Signal Independent CFT Cancellation --- p.43 / Chapter 5.2.2. --- Signal Dependent CFT Cancellation --- p.44 / Chapter 5.2.3. --- Complete CFT Cancellation --- p.45 / Chapter 5.2.4. --- CFT Cancellation by Transmission Gate --- p.45 / Chapter 5.2.5. --- CFT Cancellation by Dummy Switches --- p.47 / Chapter 5.3. --- Common Mode Feed Forward (CMFF) --- p.48 / Chapter 5.4. --- Differential Current Comparator --- p.52 / Chapter 5.4.1. --- Regenerative Latch --- p.53 / Chapter 5.4.2. --- Pre-amplifier --- p.54 / Chapter 5.5. --- Residual Generator --- p.55 / Chapter 5.6. --- Thermometer to Binary code Decoder --- p.57 / Chapter 6. --- Layout Considerations --- p.59 / Chapter 6.1. --- Overview --- p.59 / Chapter 6.2. --- Process Introduction --- p.59 / Chapter 6.3. --- Common Centroid Layout --- p.60 / Chapter 6.4. --- The Design of Power Supply Rails --- p.63 / Chapter 6.5. --- Shielding --- p.64 / Chapter 6.6. --- Layout of the whole design --- p.65 / Chapter 7. --- Simulation Results --- p.67 / Chapter 7.1. --- Overview --- p.67 / Chapter 7.2. --- Simulation Results of the Current Sample-and-Hold --- p.67 / Chapter 7.3. --- Simulation Results of the Differential Current Comparator --- p.70 / Chapter 7.4. --- Simulation Results of the overall ADC using One-Stage Simulation Result --- p.71 / Chapter 7.5. --- Power Simulation of the Overall 12-Bit ADC --- p.75 / Chapter 7.6. --- Summary --- p.78 / Chapter 8. --- Measurement Results --- p.79 / Chapter 8.1. --- Overview --- p.79 / Chapter 8.2. --- PCB Design Consideration --- p.79 / Chapter 8.3. --- Measurement Setup --- p.82 / Chapter 8.4. --- Measurement Result --- p.84 / Chapter 8.4.1. --- Static Parameters --- p.84 / Chapter 8.4.2. --- Frequency Domain Measures --- p.85 / Chapter 8.5. --- Discussion --- p.90 / Chapter 9. --- Conclusion --- p.95 / Chapter 9.1. --- Research Methodology of this Project --- p.95 / Chapter 9.2. --- Comparison between Voltage Mode and Current Mode Circuit --- p.97 / Chapter 9.3. --- Contribution of this Project --- p.98 / Chapter A. --- Appendices --- p.99 / Chapter A.I. --- Small Signal Analysis on CMMC and FG Memory Cell --- p.99 / Chapter A.II. --- The ESD Protection on the ADC --- p.102 / Chapter A.III. --- The Histogram Test to determine the DNL and INL of ADC --- p.104 / Chapter A.IV. --- Measurement Result of a Commercially Available ADC AD7820 --- p.106 / Chapter A.V. --- Pin Assignment of the Current Mode ADC --- p.109 / Chapter A.VI. --- Schematics of the Current Mode ADC --- p.111 / Chapter A.VII. --- The Chip Micrograph --- p.113 / Bibliography --- p.114

在過去的幾十年中，無線通信已經歷了顯著的發展，並成為日常生活中必不可少的一部分。隨著對可移動便攜式電子設備的需求不斷增加，功耗已经成為射頻前端電路設計的一個最關鍵參數。在便攜式無線消費類電子中，頻率綜合器在收发机设计中提供本地振盪器（LO），它又是一個高功耗的子系統之一。降低頻率綜合器的功耗將會直接影响電池的使用時間。 / 為了驗證進來新型的低功耗技术，本文基於低成本的0.18微米三阱CMOS工藝，設計並實現了三個不同的電路模塊和一個頻率綜合器系統。第一個設計是一個低壓正交壓控振盪器(QVCO)和除肆分頻器的電流復用電路。在沒有損耗電壓餘量的情況下，兩個高頻模塊通過電流復用的方式，從而降低了功耗。測試結果顯示當電源電壓為1.3V ，電流消耗電流為2.7毫安。在2.2 GHz載波附近1MHz頻偏位置上的相位噪聲為 -114 dBc/Hz。第二個設計是應用於SDR的變壓器和電流復用的壓控振盪器/分頻器的電路。該電路通過調整偏置電壓，僅用一個分頻器就可以實現可變分頻比（2，3，…,9）的功能。實驗結果表明，分頻器的輸出頻率範圍從0.58至3.11 GHz，在5.72 GHz載波附近1MHz頻偏位置上的相位噪聲為-112.5 dBc / Hz，電源電壓為1.8V時，電流為4.7mA。第三個設計是應用於UWB的變壓器和電流復用的QVCO / SSBM電路。這個全新的結構電路面積為0.8平方毫米，在1.6V電源電壓下，消耗功耗約為11 mA。測量結果表明，帶外雜散抑制小於43dBc，頻率偏移1MHz位置處的相位噪聲小於-112 dBc/Hz。最後一個設計是應用於 MB-OFDM UWB的頻率綜合器。這個新結構只用了一個電感在不犧牲主要性能的情況下，可以實現小的芯片尺寸和低的功耗。測試結果全部基於UWB的頻段，相位噪聲為-119 dBc/Hz@10 MHz，電源電壓1.2 V，總電流消耗為24.7mA。 / Over the past decades, wireless communication has experienced a remarkable development and become an essential part of daily life. With the rapid increasing demand for mobile and portable electronic devices, the power dissipation has become one of the most critical design parameters, especially for RF front-ends. In portable wireless consumer electronics, the RF frequency synthesizer is one of the most power-consuming subsystems, which serves as local oscillator (LO) in transceiver design. Any power saving in frequency synthesizer will directly affect the running time of battery. / To demonstrate recent innovation in low power techniques, three different circuit blocks and one frequency synthesizer have been developed and fabricated in low-cost 0.18μm triple-well CMOS process. The first design is a low-voltage current reused quadrature VCO and divider-by-4 frequency divider circuit. By the novel sharing of transistors between the two high frequency blocks, the power consumption of the overall design can be reduced with little penalty on voltage headroom. Experimental results show a phase noise level of -114 dBc/Hz at 1 MHz offset from 2.2 GHz carrier and consumes 2.7 mA from a 1.3V power supply. The second design is a transformer-based current reused VCO/ILFD circuits for SDR application. By the adoption of bias tuning techniques, variable division ratios (2,3,…,9) can be achieved with a single divider circuit. Experimental results show an output frequency ranging from 0.58 to 3.11 GHz and a phase noise level of -112.5 dBc/Hz at 1 MHz offset from 5.72 GHz carrier, with a consumed current of 4.7 mA from a 1.8V power supply. The third design is a transformer-based current-reused QVCO/SSBM circuit for UWB application. The prototype is the first of its kind, while occupies a core area of 0.8 mm² and consumes roughly 11 mA from 1.6V power supply. Measurement results show that the out-of-band spurious rejection and phase noise at 1 MHz offset are better than 43 dBc and -112 dBc/Hz respectively. The final design is a frequency synthesizer for MB-OFDM UWB application. It uses a single inductor approach and novel system architecture to realize compact die size and low power consumption without sacrificing major performance. Experimental results show a phase noise level of -119 dBc/Hz@10 MHz offset for all UWB bands and consumes 24.7 mA from a 1.2 V power supply. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Wei. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.xi / List of Table --- p.xvi / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Outline of Dissertation --- p.3 / References --- p.5 / Chapter CHAPTER 2 --- A NOVEL LOW-VOLTAGE CURRENT REUSED, QUADRATURE VCO AND DIVIDE-BY-4 FREQUENCY DIVIDER --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Oscillation Principle of VCO --- p.9 / Chapter 2.3 --- Circuit Implementation --- p.14 / Chapter 2.3.1 --- Back-gate Coupled QVCO --- p.14 / Chapter 2.3.2 --- Divider-by-4 Frequency Divider --- p.20 / Chapter 2.3.3 --- Current Reuse QVCO and Frequency Divider --- p.24 / Chapter 2.3.3.1 --- Voltage Headroom --- p.25 / Chapter 2.3.3.2 --- Startup Condition --- p.26 / Chapter 2.3.3.3 --- Operating Range --- p.27 / Chapter 2.3.3.4 --- Phase Noise --- p.28 / Chapter 2.3.3.5 --- Transient Response --- p.30 / Chapter 2.4 --- Experimental Result --- p.31 / Chapter 2.4.1 --- Frequency Tuning Range --- p.32 / Chapter 2.4.2 --- Phase Noise --- p.33 / Chapter 2.4.3 --- Transient Response --- p.34 / Chapter 2.4.4 --- Performance Comparison --- p.34 / Chapter 2.5 --- Summary --- p.36 / Reference --- p.36 / Chapter CHAPTER 3 --- A TRANSFORMER BASED CURRENT REUSED VCO/ILFD CIRCUIT WITH VARIABLE DIVIDING RATIOS --- p.41 / Chapter 3.1 --- Introduction --- p.41 / Chapter 3.2 --- Transformer Design --- p.43 / Chapter 3.2.1 --- Ideal Transformer --- p.43 / Chapter 3.2.2 --- Transformer Tank --- p.45 / Chapter 3.3 --- Design of Current Reused VCO/ILFD --- p.49 / Chapter 3.3.1 --- Transformer Implement --- p.50 / Chapter 3.3.2 --- VCO Implement --- p.52 / Chapter 3.3.3 --- ILFD Implement --- p.54 / Chapter 3.4 --- Experiment Results --- p.60 / Chapter 3.4.1 --- Phase Noise --- p.61 / Chapter 3.4.2 --- Frequency Tuning Range --- p.62 / Chapter 3.4.3 --- Transient Response --- p.64 / Chapter 3.4.4 --- Performance Comparison --- p.65 / Chapter 3.5 --- Summary --- p.66 / Reference --- p.66 / Chapter CHAPTER --- 4 CURRENT REUSED QVCO/SSBM CIRCUIT FOR MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.70 / Chapter 4.1 --- Introduction --- p.70 / Chapter 4.2 --- Proposed solution for UWB frequency synthesizer --- p.72 / Chapter 4.3 --- Bimodal Oscillation Phenomenon --- p.74 / Chapter 4.4 --- Design of Current Reused QVCO/SSBM Circuit --- p.81 / Chapter 4.4.1 --- Transformer Implementation --- p.82 / Chapter 4.4.2 --- QVCO Implementation --- p.85 / Chapter 4.4.3 --- SSBM Implementation --- p.88 / Chapter 4.5 --- Experimental Results --- p.89 / Chapter 4.5.1 --- Phase Noise --- p.91 / Chapter 4.5.2 --- Spur Suppression --- p.92 / Chapter 4.5.3 --- Performance Comparison --- p.93 / Chapter 4.6 --- Summary --- p.94 / Reference --- p.95 / Chapter CHAPTER 5 --- A SINGLE INDUCTOR APPROACH TO THE DESIGN OF LOW-VOLTAGE MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.98 / Chapter 5.1 --- Introduction --- p.98 / Chapter 5.2 --- Frequency Synthesizer Background --- p.101 / Chapter 5.2.1 --- General Consideration --- p.101 / Chapter 5.2.1.1 --- Frequency Requirement --- p.102 / Chapter 5.2.1.2 --- Phase Noise --- p.103 / Chapter 5.2.1.3 --- Spurious Tones --- p.104 / Chapter 5.2.1.4 --- Switching Time --- p.105 / Chapter 5.2.2 --- Overview of MB-OFDM UWB Frequency Synthesizer --- p.105 / Chapter 5.3 --- Frequency Synthesizer System Design --- p.109 / Chapter 5.3.1 --- Proposed Frequency synthesizer Architecture --- p.109 / Chapter 5.3.2 --- Stability Analysis --- p.111 / Chapter 5.3.3 --- Phase Noise Contribution --- p.115 / Chapter 5.4 --- Circuit Implementation --- p.121 / Chapter 5.4.1 --- Current Reused Multiplier/SSBM --- p.121 / Chapter 5.4.2 --- 12-Phase Cross-coupled Ring VCO --- p.128 / Chapter 5.4.3 --- Regenerative Frequency Divider --- p.131 / Chapter 5.4.4 --- Tri-mode Phase Calibration Buffer --- p.132 / Chapter 5.4.5 --- Phase-Frequency Detector(PFD) --- p.134 / Chapter 5.4.6 --- Charge Pump --- p.135 / Chapter 5.4.7 --- CML Divider --- p.136 / Chapter 5.5 --- Experimental Result --- p.137 / Chapter 5.5.1 --- Frequency Tuning Range --- p.139 / Chapter 5.5.2 --- Phase Noise --- p.140 / Chapter 5.5.3 --- Spur Suppression --- p.141 / Chapter 5.5.4 --- Performance Comparison --- p.142 / Chapter 5.6 --- Summary --- p.143 / Reference --- p.143 / Chapter CHAPTER 6 --- CONCLUSIONS AND FUTURE WORKS --- p.147 / Chapter 6.1 --- Conclusions --- p.147 / Chapter 6.2 --- Future Works --- p.149 / List of Publication --- p.150

Cheng Wang Chi. / "October 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 135-139) / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

by Cheng Wang Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 108-111). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgments --- p.v / Contents --- p.vii / List of Tables --- p.xiii / List of Figures --- p.xiv / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Technical Challenges of CMOS RF Design --- p.2 / Chapter 1.3 --- General Background --- p.2 / Chapter 1.3.1 --- Bipolar and CMOS Mixers --- p.4 / Chapter 1.4 --- Research Goal --- p.4 / Chapter 1.5 --- Thesis Outline --- p.5 / Chapter Chapter2 --- RF Fundamentals --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Frequency Translation --- p.6 / Chapter 2.3 --- Conversion Gain --- p.8 / Chapter 2.4 --- Linearity --- p.8 / Chapter 2.4.1 --- 1-dB Compression Point --- p.11 / Chapter 2.4.2 --- Third Intercept Point (IP3) --- p.11 / Chapter 2.5 --- Dynamic Range (DR) --- p.13 / Chapter 2.5.1 --- Spurious-Free Dynamic Range (SFDR) --- p.13 / Chapter 2.5.2 --- Blocking Dynamic Range (BDR) --- p.14 / Chapter 2.6 --- Blocking and Desensitization --- p.15 / Chapter 2.7 --- Port-to-Port Isolation --- p.15 / Chapter 2.8 --- Single-Balanced and Double-Balanced Mixers --- p.16 / Chapter 2.9 --- Noise --- p.16 / Chapter 2.9.1 --- Noise in the Local Oscillator --- p.17 / Chapter 2.9.2 --- Noise Figure --- p.18 / Chapter Chapter3 --- Downconversion Mixer --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Review of Mixer Topology --- p.19 / Chapter 3.2.1 --- Square-Law Mixer --- p.20 / Chapter 3.2.2 --- CMOS Gilbert Cell --- p.21 / Chapter 3.2.3 --- Potentiometric Mixer --- p.22 / Chapter 3.2.4 --- Subsampling Mixer --- p.23 / Chapter Chapter4 --- Proposed Downconversion Mixer --- p.24 / Chapter 4.1 --- Analysis of Proposal Mixer --- p.24 / Chapter 4.2 --- Current Folded Mirror Mixer --- p.24 / Chapter 4.2.1 --- Operating Principle --- p.25 / Chapter 4.2.2 --- Large Signal Analysis --- p.26 / Chapter 4.2.3 --- Small Signal Analysis --- p.29 / Chapter 4.3 --- Current Mode Mixer --- p.32 / Chapter 4.3.1 --- Operating Principle --- p.33 / Chapter 4.3.2 --- Large Signal Analysis --- p.33 / Chapter 4.3.3 --- Small Signal Analysis --- p.34 / Chapter 4.3.4 --- V-I Converter --- p.36 / Chapter 4.3.4.1 --- Equation Analysis --- p.37 / Chapter 4.4 --- Second Order Effects --- p.38 / Chapter 4.4.1 --- Device Mismatch --- p.38 / Chapter 4.4.2 --- Body Effect --- p.39 / Chapter 4.5 --- Single-ended to Differential-ended converter --- p.39 / Chapter 4.6 --- Output Buffer Stage --- p.40 / Chapter 4.7 --- Noise Theory --- p.41 / Chapter 4.7.1 --- SSB and DSB Noise Figure --- p.42 / Chapter 4.7.2 --- Noise Figure --- p.43 / Chapter Chapter5 --- Simulation Results --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Current Folded Mirror Mixer --- p.44 / Chapter 5.2.1 --- Conversion Gain --- p.45 / Chapter 5.2.2 --- Linearity --- p.46 / Chapter 5.2.2.1 --- 1dB Compression Point and IIP3 --- p.49 / Chapter 5.2.3 --- Output Buffer Stage --- p.49 / Chapter 5.3 --- Current Mode Mixer --- p.51 / Chapter 5.3.1 --- Conversion Gain --- p.51 / Chapter 5.3.2 --- Linearity --- p.52 / Chapter 5.3.2.1 --- 1-dB Compression Point and IIP3 --- p.52 / Chapter 5.3.3 --- Output Buffer Stage --- p.53 / Chapter 5.3.4 --- V-I Converter --- p.54 / Chapter 5.4 --- Single-ended to Differential-ended Converter --- p.55 / Chapter Chapter6 --- Layout Consideration --- p.57 / Chapter 6.1 --- Introduction --- p.57 / Chapter 6.2 --- CMOS transistor Layout --- p.57 / Chapter 6.3 --- Resistor Layout --- p.59 / Chapter 6.4 --- Capacitor Layout --- p.60 / Chapter 6.5 --- Substrate Tap --- p.62 / Chapter 6.6 --- Pad Layout --- p.63 / Chapter 6.7 --- Analog Cell Layout --- p.64 / Chapter Chapter7 --- Measurements --- p.65 / Chapter 7.1 --- Introduction --- p.65 / Chapter 7.2 --- Downconversion mixer --- p.66 / Chapter 7.3 --- PCB Layout --- p.66 / Chapter 7.4 --- Test Setups --- p.68 / Chapter 7.4.1 --- Measurement Setup for S-Parameter --- p.68 / Chapter 7.4.2 --- Measurement Setup for 1-dB Compression Point and IIP3 --- p.70 / Chapter 7.5 --- Measurement Result of the Current Folded Mirror Mixer --- p.72 / Chapter 7.5.1 --- S-Parameter Measurement --- p.75 / Chapter 7.5.2 --- Conversion Gain and the Effect of the IF Variation --- p.77 / Chapter 7.5.3 --- 1-dB Compression Point --- p.78 / Chapter 7.5.4 --- IIP3 --- p.79 / Chapter 7.5.5 --- LO Power Effect to the Mixer --- p.81 / Chapter 7.5.6 --- Performance Summaries of the Current Folded Mirror Mixer --- p.82 / Chapter 7.5.7 --- Discussion --- p.83 / Chapter 7.6 --- Measurement Result of the Current Mode Mixer --- p.84 / Chapter 7.6.1 --- S-Parameter Measurement --- p.87 / Chapter 7.6.2 --- Conversion Gain and the Effect of the IF Variation --- p.89 / Chapter 7.6.3 --- 1-dB Compression Point --- p.90 / Chapter 7.6.4 --- IIP3 --- p.91 / Chapter 7.6.5 --- LO Power Effect to the Mixer --- p.93 / Chapter 7.6.6 --- Performance Summaries of the Current Mode Mixer --- p.94 / Chapter 7.6.7 --- Discussion --- p.95 / Chapter 7.7 --- Measurement Result of the Single-ended to Differential-ended converter --- p.96 / Chapter 7.7.1 --- Measurement Setup for the Phase Difference --- p.97 / Chapter 7.7.2 --- Phase Difference Measurement --- p.98 / Chapter 7.7.3 --- Discussion --- p.99 / Chapter Chapter8 --- Conclusion --- p.100 / Chapter Appendix A --- Characteristics of the Gilbert Quad Pair --- p.102 / Chapter A.1 --- Large-Signal Analysis --- p.102 / Chapter Appendix B --- Characteristics of the V-I Converter --- p.105 / Chapter B.1 --- Large-Signal Analysis --- p.105 / Bibliography --- p.108

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception.

Chow, Chun Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 82-89). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background and Motivation --- p.1 / Chapter 1.2 --- Objective --- p.2 / Chapter 1.3 --- Contributions --- p.2 / Chapter 1.4 --- Organization of the Dissertation --- p.3 / Chapter 2 --- Carbon Nanotubes as Sensing Elements --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Introduction to Carbon Nanotubes --- p.5 / Chapter 2.3 --- Fabrication of Single Carbon Nanotube Sensors --- p.6 / Chapter 2.4 --- Batch Fabrication of CNT Sensors using Dielectrophoretic Force --- p.7 / Chapter 2.4.1 --- Basic CNTs Sensor Fabrication Process using DEP Process --- p.7 / Chapter 2.4.2 --- Modification of Fabrication Process --- p.9 / Chapter 2.5 --- Noise in Resistors --- p.9 / Chapter 2.5.1 --- Thermal Noise in Traditional Resistors --- p.10 / Chapter 2.5.2 --- Flicker Noise (1/f )Noise in Traditional Resistors --- p.11 / Chapter 2.6 --- Noise in CNTs Resistors --- p.11 / Chapter 2.6.1 --- Literature Review --- p.11 / Chapter 2.6.2 --- Noise in CNT Sensors Fabricated using DEP Process --- p.12 / Chapter 2.7 --- CNT Sensors --- p.16 / Chapter 2.7.1 --- Pressure Sensors --- p.17 / Chapter 2.7.2 --- Fluid-Flow Sensors --- p.18 / Chapter 2.7.3 --- Alcohol Sensors --- p.18 / Chapter 2.8 --- CNT Sensor Response --- p.19 / Chapter 2.8.1 --- Traditional Sensor Response Measurement Techniques . . . --- p.19 / Chapter 2.9 --- Accuracy of CNT Sensor System --- p.22 / Chapter 2.10 --- Summary --- p.24 / Chapter 3 --- Design and Analysis of a CNT-CMOS Integrated Sensor --- p.25 / Chapter 3.1 --- Introduction --- p.25 / Chapter 3.2 --- Introduction to CNT-CMOS Integration --- p.26 / Chapter 3.2.1 --- Difficulties with Commercial CNT Sensors --- p.26 / Chapter 3.2.2 --- Novel Idea for CNT-CMOS Integration --- p.26 / Chapter 3.3 --- Design and Analysis of a CNT-CMOS Sensor Prototype --- p.27 / Chapter 3.3.1 --- Goals of CNT-CMOS Integrated Sensor --- p.27 / Chapter 3.3.2 --- Architecture of CNT-CMOS Sensor --- p.28 / Chapter 3.3.3 --- Programmable Current Source --- p.29 / Chapter 3.3.4 --- Dual Slope ADC --- p.41 / Chapter 3.3.5 --- Power Consumption of CNT-CMOS IC --- p.53 / Chapter 3.3.6 --- Electrodes for CNT Sensor Formation --- p.53 / Chapter 3.3.7 --- Electrostatic Discharge Protection and Layout of Prototype --- p.56 / Chapter 3.4 --- Alcohol Tester --- p.60 / Chapter 3.4.1 --- Operation of Alcohol Tester --- p.60 / Chapter 3.5 --- Summary --- p.61 / Chapter 4 --- Results --- p.63 / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Chip Package and Photography --- p.63 / Chapter 4.3 --- Results from Programmable Current Source --- p.65 / Chapter 4.3.1 --- Temperature Coefficient --- p.65 / Chapter 4.3.2 --- Output Resistance --- p.66 / Chapter 4.4 --- Results from Dual Slope ADC --- p.67 / Chapter 4.5 --- Power consumption of the Integrated Circuit --- p.72 / Chapter 4.6 --- CNT Sensor Formation --- p.72 / Chapter 4.6.1 --- Noise Measurement of CNT-CMOS Integrated Sensor --- p.76 / Chapter 4.7 --- Alcohol Tester Results --- p.76 / Chapter 4.7.1 --- Carbon Resistor --- p.77 / Chapter 4.8 --- Summary --- p.77 / Chapter 5 --- Conclusion --- p.79 / Chapter 5.1 --- Future Work --- p.80 / Chapter 5.1.1 --- Detailed CNT Noise Characterization --- p.80 / Chapter 5.1.2 --- High Frequency CNT Measuring Technique --- p.81 / Chapter 5.1.3 --- Higher Degree of CMOS Integration --- p.81 / Chapter 5.2 --- Concluding Remarks --- p.81 / Bibliography --- p.82 / A Schematic Diagram of ADC Testing --- p.90