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Design of sample and holds using CCDs in a standard CMOS processGhatak, Kalyan Brata 07 August 2002 (has links)
The parasitic components of MOS switches at high speeds affect the linearity
and resolution of CMOS sample and hold circuits. CCD-based circuit design can
offer good performance at high speeds. This thesis presents the design of sample
and hold circuits using charge-coupled device structures in a standard CMOS process.
Three sample and hold circuits have been built and tested for linearity and
speed performance. The CCD S/Hs have been characterized using a continuous-time
integrator and a Δ∑ ADC. The CCDs, with a switched capacitor amplifier
at the output, achieve an SFDR of 54dB for an input signal V[subscript in]=2.6V+0.4Vpp at
f[subscript in]=10.1KHz. / Graduation date: 2003
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Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substratesSharma, Ajit 31 July 2003 (has links)
This thesis presents an automated methodology to calibrate the substrate
profile for accurate prediction of substrate parasitics using Green's function based
extractors. The technique requires fabrication of only a few test structures and results
in an accurate three layered approximation of a heavily doped epitaxial silicon
substrate. The obtained substrate resistances are accurate to about 10% of measurements.
Advantages and limitations of several common measurement techniques
used to measure substrate z-parameters and resistances are discussed. A new and
accurate z-parameter based macro-model has been developed that can be used up
to a few GHz for P��� for contacts that are as close as 2��m. This enhanced model also
addresses the limitations of previous models with regards to implementation aspects
and ease of integration in a CAD framework. Limitations of this modeling approach
have been investigated. The calibration methodology can be used along with the
scalable macromodel for a qualitative pre-design and pre-layout estimation of the
digital switching noise that couples though the substrate to sensitive analog/RF
circuits. / Graduation date: 2004
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Low frequency noise and the upconverted phase noise effects in NMOSFET circuitsXie, Dingming 14 October 1999 (has links)
Graduation date: 2000
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Design and computer aided optimization of a fully integrated CMOS RF distributed amplifierBallweber, Brian M. 13 November 1998 (has links)
Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major challenges facing circuit designers is the difficulty in implementing high frequency RF analog circuits on these types of technologies. Analog circuits which make use of parasitic-laden components such as inductors are especially difficult to realize.
The purpose of this thesis is to investigate the design and application of an optimization tool based on simulated annealing to this type of problem. The goal is to have the optimizer incorporate these unavoidable component parasitics into a design, and thus eliminate any undesirable performance degradation.
The optimization technique will be applied to the design of a CMOS RF distributed amplifier. This type of amplifier has a flat gain characteristic over an exceptionally wide bandwidth, and it is heavily reliant on inductive structures. Historically, an amplifier of this type has never been implemented on a standard CMOS process, without the use of bondwire inductances or special processing techniques. However, it will be shown in this thesis that, with the aid of the optimization technique, a distributed amplifier
design can be successfully realized on a standard CMOS process. / Graduation date: 1999
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Low-power high-performance 32-bit 0.5[u]m CMOS adderShah, Parag Shantu 08 July 1998 (has links)
Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power product(SPP). 32-bit CMOS adders are used as representative circuits to investigate a method of
reducing the SPP. The purpose of this thesis is to show that sizing gates according to fan-out and removing buffer drivers can reduce the SPP. This thesis presents a method for sizing gates in large fan-out parallel prefix circuits to reduce the SPP and compares it to
other methods. Three different parallel prefix adders are used to compare propagation delay and SPP. The first adder uses the depth-optimal prefix circuit. The second adder is based on Wei, Thompson, and Chen's time-optimal adder. The third adder uses a recursive doubling formation where all cells have minimum transistor width dimensions. The component cells in the adders are static CMOS as described by Brent and Kung. For all circuits, the smallest propagation delay occurs when the highest voltage supply is
applied. The smallest SPP occurs when the lowest voltage supply is applied, but with the lowest performance. The Recursive Doubling Adder always has the lowest propagation delay for a particular set of parameters. However, its SPP is nearly equal to the Brent-Kung Adders and lower than Wei's Adder. The power-frequency analysis reveals that a decrease in Vt causes higher power consumption due to leakage. / Graduation date: 1999
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High-linearity switched-capacitor circuits in digital CMOS technologiesYoshizawa, Hirokazu 15 May 1997 (has links)
In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction of distortion, two capacitors can be connected in series or in parallel so that a first-order cancellation of the nonlinearity can be achieved. Experimental results demonstrated that the among these techniques series compensation is the most effective for reducing the nonlinearity of MOSFET capacitors.
A novel predictive SC amplifier has been proposed for its insensitivity to op-amp imperfections. Experimental results show that the S/THD of the predictive SC amplifier was 10 dB larger than that of the non-predictive one. It was also shown that a predictive circuit was effective for reducing the nonlinearity caused by the op-amp and/or the MOSFET capacitors.
It has been demonstrated that a two-stage op-amp with a large output swing can be fabricated in a standard digital CMOS process. The frequency compensation was accomplished using a source follower and a MOSFET capacitor. An SC amplifier using this two-stage op-amp and double-poly capacitors was fabricated, and it exhibited a large linear output range.
A MOSFET-only digitally controlled gain/loss circuit was designed and fabricated in a 1.2�� CMOS process. It demonstrated that the series compensation is effective not only for a large output swing in an amplifier, but also for a large input swing in an attenuator.
A pipeline D/A converter utilizing MOSFET capacitors was designed as another application of charge processing technique. It consisted of three parts: a V-Q conversion stage, a charge transfer stage, and a Q-V converter.
A new switch configuration which enables the series compensation to have a large bias voltage has also been proposed. It was shown that it works well, and it will be helpful for low-voltage operation, too. / Graduation date: 1998
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Suppression of substrate noise in a mixed-signal CMOS intergrated circuitLim, Wei Tjan (Richard) 29 May 1996 (has links)
Substrate switching noise is becoming a concern as integrated circuits get larger
and speeds get faster. Mixed-mode integrated circuits are especially affected as the
substrate noise interferes with sensitive analog circuits resulting in limited signal to noise
ratios. This thesis serves to study the cause of the noise at the point where it is generated
to the way it propagates to the analog circuits, and presents several approaches to reduce
the switching noise. In addition, it examines the substrate impedance as being a key
element to successful and reliable design for low-noise CMOS mixed-signal integrated
circuits. Utilizing the substrate lead inductance and current-variable capacitances through
the use of guard ring diodes, resonant frequencies which provide a low impedance path to
ground are created. These can be tuned to coincide with problematic noise frequency
components or to cancel the pin and package resonance, thus suppressing noise and
improving reliability. / Graduation date: 1997
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Design of a True-Q Flip FlopHui, Henry 20 October 1994 (has links)
A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as
an asynchronous storage element in micropipelines or a part of the synchronizer. It is
capable of double-edge triggering which latches data at both the rising and the trailing
edges. It is also free of the metastability state problem.
Some analog and digital circuits are incorporated with a true double-edge triggered
Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an
acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding
stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the
flip flop will not be received by the next stage if Q is in a metastable state.
The number of transistors used in this implementation of True-Q flip flop is 90. Due
to the overhead of circuit complexity, the time delay from Request to Acknowledge signal
is 6.5ns. / Graduation date: 1995
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Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistorsHwang, Nam 29 November 1993 (has links)
Graduation date: 1994
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Novel channel materials for Si based MOS devices: Ge, strained Si and hybrid crystal orientations28 August 2008 (has links)
Not available
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