Planarization techniques such as Surface planer (better known as Fly-cut) and chemical-mechanical polishing (CMP) can be used to improve the bump roughness and bump height uniformity within the die and wafer which can be beneficial for solder based bump stacking and Cu-Cu direct bonding [1]. In this paper the influence of both planarization techniques on 20μm pitch Cu and CuNiSn bumps embedded in polymer are studied. The polymer protects the bumps from the shearing force of the planarization process and will later serve as a underfill material for the resulting gap of a 3D stack. The microbump planarization process will be discussed. Furthermore characterization of the bump height uniformity across the wafer using SEM and High Resolution Profilometry (HRP) is reported.

In this paper SAM (self-assembled monolayers) is used to passivate cobalt microbumps for 3D-stacking of Si chips. The SAM deposition process is optimized, using input from characterization techniques such as water contact angle measurement, ATR, AFM and XPS analysis in order to form a monolayer of Thiols-SAM on cobalt microbumps. A 3D stacked Si chips test vehicle was used to demonstrate the effectiveness of the SAM coating on cobalt bumps by measuring the electrical continuity of daisy chains.

Planarization techniques such as Surface planer (better known as Fly-cut) and chemical-mechanical polishing (CMP) can be used to improve the bump roughness and bump height uniformity within the die and wafer which can be beneficial for solder based bump stacking and Cu-Cu direct bonding [1]. In this paper the influence of both planarization techniques on 20μm pitch Cu and CuNiSn bumps embedded in polymer are studied. The polymer protects the bumps from the shearing force of the planarization process and will later serve as a underfill material for the resulting gap of a 3D stack. The microbump planarization process will be discussed. Furthermore characterization of the bump height uniformity across the wafer using SEM and High Resolution Profilometry (HRP) is reported.

In this paper SAM (self-assembled monolayers) is used to passivate cobalt microbumps for 3D-stacking of Si chips. The SAM deposition process is optimized, using input from characterization techniques such as water contact angle measurement, ATR, AFM and XPS analysis in order to form a monolayer of Thiols-SAM on cobalt microbumps. A 3D stacked Si chips test vehicle was used to demonstrate the effectiveness of the SAM coating on cobalt bumps by measuring the electrical continuity of daisy chains.