In this paper SAM (self-assembled monolayers) is used to passivate cobalt microbumps for 3D-stacking of Si chips. The SAM deposition process is optimized, using input from characterization techniques such as water contact angle measurement, ATR, AFM and XPS analysis in order to form a monolayer of Thiols-SAM on cobalt microbumps. A 3D stacked Si chips test vehicle was used to demonstrate the effectiveness of the SAM coating on cobalt bumps by measuring the electrical continuity of daisy chains.

Bumpless interconnects and ultra-thinning of 300 mm wafers for three-dimensional (3D) stacking technology has been studied [1, 2]. In our previous studies, wafer thinning effect using device wafers less than 10 μm was investigated [3, 4]. There was no change for the retention time before and after thinning even at 4 μm in thickness of DRAM wafer [5]. In this study, the behavior of Cu contamination on an ultra-thin Si stacked structure was investigated. Thinned Si wafers were intentionally contaminated with Cu on the backside and 250 °C of heating was carried out during the adhesive bonding and de-bonding processing. An approximately 200 nm thick damaged layer was formed at the backside of the Si wafer after thinning process and Cu particle precipitates ranged at 20 nm were observed by cross-sectional transmission electron microscopy (X-TEM). With secondary ion mass spectrometry (SIMS) and EDX analyses, Cu diffusion was not detected in the Si substrate, suggesting that the damaged layer prevents Cu diffusion from the backside.

The task of my thesis was to automate the process of 3D stacking. The work includes design of complex control board, that will serve as a control unit and provide a comprehensive function of mechanical displacement in combination with digital image acquisition. In addition, the electronics for controlling a stepper motor, PCB and the design. The result of this is a facility that provides automatic acquisition of images with different depth of field.

In this paper SAM (self-assembled monolayers) is used to passivate cobalt microbumps for 3D-stacking of Si chips. The SAM deposition process is optimized, using input from characterization techniques such as water contact angle measurement, ATR, AFM and XPS analysis in order to form a monolayer of Thiols-SAM on cobalt microbumps. A 3D stacked Si chips test vehicle was used to demonstrate the effectiveness of the SAM coating on cobalt bumps by measuring the electrical continuity of daisy chains.

Bumpless interconnects and ultra-thinning of 300 mm wafers for three-dimensional (3D) stacking technology has been studied [1, 2]. In our previous studies, wafer thinning effect using device wafers less than 10 μm was investigated [3, 4]. There was no change for the retention time before and after thinning even at 4 μm in thickness of DRAM wafer [5]. In this study, the behavior of Cu contamination on an ultra-thin Si stacked structure was investigated. Thinned Si wafers were intentionally contaminated with Cu on the backside and 250 °C of heating was carried out during the adhesive bonding and de-bonding processing. An approximately 200 nm thick damaged layer was formed at the backside of the Si wafer after thinning process and Cu particle precipitates ranged at 20 nm were observed by cross-sectional transmission electron microscopy (X-TEM). With secondary ion mass spectrometry (SIMS) and EDX analyses, Cu diffusion was not detected in the Si substrate, suggesting that the damaged layer prevents Cu diffusion from the backside.