Thesis (Ph.D.)--Ohio University, November, 2004. / Title from PDF t.p. Includes bibliographical references (p. 202-211)

Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisor: John G. Ekerdt. Vita. Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Systems Science, 2005. / Includes bibliographical references.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references (leaves 97-107). Also available in electronic version.

Thesis (Ph. D.)--University of Missouri-Columbia, 1999. / Typescript. Vita. Includes bibliographical references (leaves 182-186). Also available on the Internet.

see document / Master of Science

Polyimides are one class of high temperature materials that have been extensively used in the microelectronics industry in passivation and protection. The extremely good thermal stabilities, along with desirable mechanical and electrical properties, have led to their use in integrated circuits and thin film multi-layer packaging. Due to rapid advances in the microelectronics industry, stringent demands have been placed on the improvement of electric performance of the packaging systems. This has resulted in a search for materials with extremely low dielectric constants while maintaining the desirable thermal and mechanical properties. In the past, the incorporation of fluorine into polyimides has been shown to decrease the dielectric constant. In this research, the concept of a foamed morphology has been utilized to obtain a decrease in the dielectric constant, by taking advantage of the low value for air. To achieve compatibility with the microscopic features of the electronic circuitry, polyimide foams with pore sizes in the nanometer regime have been developed. Block and graft copolymers consisting of thermally stable polyimide and labile poly(propylene oxide) were synthesized to first develop the desired microphase separated morphology. Both semicrystalline and fluorinated polyimides were evaluated as low dielectric matrices with improved mechanical properties and solvent resistance. The labile component was degraded with thermal treatment in air, leaving behind pores where the size and shape were largely determined by the original multiphase copolymer morphology. / Ph. D.

Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².

The microelectronics industry strives for continued reduction in feature sizes to allow increased computing speed and power. This calls for continuous development of new materials. During the shift to 157 nm photolithography, it was discovered that fluorinated materials were necessary to provide sufficient transparency. Material design and synthesis to incorporate fluorine bearing norbornane based materials through an alternate means of polymerization to those used in traditional lithographic materials will be presented. Step and Flash Imprint Lithography represents a low cost alternative to optical lithography for production of nanoscale features. Sub-20 nm features have been produced using commercial tools however the contact between the imprint template and resist formulation leaves the template prone to fouling. A new imprint resist designed to facilitate wafer reworking and template cleaning is presented. The small amount of power available from deep ultraviolet light sources necessitates the use of systems that behave in a catalytic manner that is referred to as gain. The use of small molecules for gain necessitates a reliance on diffusion through the resist film and results in image bias. A polymeric material that undergoes depropagation catalyzed by a single photochemical event and causes a solubility change due to this event represents a system that possesses gain while removing diffusion bias. Progress towards such a system is presented. / text

Approved for Public Release; Distribution is Unlimited / This thesis developed the sample fabrication and experimental design for studying interfacial creep at thin film / Silicon interfaces. The specific interface of study was the crystalline interface created by Positive Vapor deposition of a metallic thin film on a very smooth Silicon substrate. Emphasis was placed on development and refinement of the fabrication techniques necessary to produce test samples that provide valid reproduction of the interfacial stress state in isolation from other stresses inherent in the complete device. Test sample fabrication utilized traditional laboratory methods combined with leading edge methodology in two fabrication steps; namely diffusion bonding of an Silicon substrate / PVD Aluminum thin film / Silicon substrate composite structure and micro-machining Silicon through the use of a TMAH based etchant. In conjunction with the sample development a test platform was designed, fabricated, assembled, and aligned to provide for isolated parametric characterization of the proposed interfacial creep model. The results of this characterization are anticipated to be of significant utility in improving the design for fabrication and reliability of current and next generation microelectronic and microelectro-mechanical devices. / Lieutenant Commander, United States Navy