Thesis (Ph. D.)--McMaster University, 2000. / Advisor: Raymond Findlay. Includes bibliographical references (leaves 222-228). Also available online.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 365-373). Available also in a digital version from Dissertation Abstracts.

High-frequency noise modeling and characterization of nanoscale MOSFETs are essential driving forces for highly scaled CMOS technology to be used in radio-frequency applications. Continuous downscaling increases the operating frequency of the MOSFETs, reduces the power supply voltage but does not scale noise accordingly. This makes the noise issue of future low-power technology more prominent and therefore accurate noise modeling more important. In this thesis, several important issues regarding noise modeling and characterization for nanoscale MOSFETs are studied. First, a new noise factor deembedding algorithm is proposed for on-wafer noise measurements. It solves the problem of noise factor deembedding in which the active two-port device is surrounded by a four-port parasitic network. Based on it, a new deembedding-first and optimization-last noise parameter deembedding approach is proposed and its performance is evaluated using experimental data. Second, the noise performance of modern sub-100-nm MOSFETs are evaluated using the noise sheet resistance as a figure of merit. It shows that future technologies generally have degraded noise performance. In addition, two accuracy issues regarding the calibration of noise receiver for high-frequency noise measurements are investigated and methods to mitigate these issues are discussed. Third, a novel Z-parameter based approach to extract the gate resistance is proposed for MOSFET characterization. It is evaluated against other published methods using experimental data. In addition, the extraction of the resistance of the lightly-doped-drain region and the gate contact is also performed and discussed. Finally, a new perspective to interpret the MSOFET channel noise as suppressed shot noise is presented. An easy-to-use analytical expression for the suppression factor is derived and it only relies on two process parameters – threshold voltage and effective oxide thickness – to predict the level of suppression for the channel noise of MOSFETs. It is evaluated using published experimental data on various CMOS technology nodes. / Thesis / Doctor of Philosophy (PhD)

All oxide heterostructure Cr2O3/TiO2-x was deposited on Al2O3(0001) single crystal via MBE. The analysis of interfacial interactions involving two metal oxides resulting in magnetic properties gave insights for using such heterostructures as potential spintronic device materials. The corundum phase epitaxial growth of TiO2-x on Al2O3 was characterized using XPS, AES, EELS, and LEED. The data obtained gives evidence of presence of two-dimensional electron gas at titania surface due to oxygen vacancies formation after deposition. On titania, the deposition of chrome in UHV results in the formation of oxidized chromia overlayer by abstraction of oxygen from the TiO2-x underlayer further increasing the number of vacancies present. In industrial R&D project, dry etching of multiple optical device components was performed using a novel angled etch prototype tool. The first set of experiments involved plasma etching of SiC thin films optimized for target application. The best-known method (BKM) worked from 300mm full wafer to 200mm product. In second experimentation, a variety of gray-tone photoresist received from customers were etched using BKM. Customer received etch rate on each gray-tone material. The third experiments compared recipe R1 to test recipe R2 on the test vehicle VDC. R2 showed faster etch rate but lower process repeatability (RMSE%). With continuous improvement of the tool and the process, two tools are operating products every day, a third prototype tool is about to be in pilot production.

No description available.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of System Science and Industrial Engineering, 2005. / Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 103-104).

No description available.

Approved for public release; distribution is unlimited / Large shear stresses often develop at the interface between dissimilar materials in microelectronic devices, when they are subjected to thermo-mechanical excursions. These stresses can facilitate diffusionally accommodated interfacial sliding, or creep. A driving factor for these stresses is the thermal expansion mismatch between the adjoining materials. For narrow thin film lines, these stresses may exist over a large fraction of the film-substrate interface. This thesis explores methodologies to measure the kinetics of interfacial creep at model Al thin film/silicon substrate interfaces. A method of sample production, which involved diffusion bonding a polished Si substrate to the surface of a thin Al film deposited on a second Si substrate was developed (Si/Al/Si sandwich). When loaded edge-wise in compression, the Al thin film - Si interface are loaded in shear. By measuring the relative displacements between the two Si substrates, the interfacial displacement rates at varying temperatures and stresses were experimentally determined. In accordance with previous results, the kinetics was given by a diffusional creep law with a threshold stress, and an activation energy representing interfacial diffusion. The activation energy was found to be unusually low, and further experimental and modeling studies are needed to better understand its origin. / Lieutenant Commander, United States Navy

Thesis (Ph. D.)--University of Missouri-Columbia, 1999. / Typescript. Vita. Includes bibliographical references (leaves 182-186). Also available on the Internet.